Searched refs:CLK_TOP_AUD_1_SEL (Results 1 - 24 of 24) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 89 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 116 #define CLK_TOP_AUD_1_SEL 105 macro
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| H A D | mt6765-clk.h | 148 #define CLK_TOP_AUD_1_SEL 113 macro
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| H A D | mt8173-clk.h | 119 #define CLK_TOP_AUD_1_SEL 109 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mt2712-clk.h | 156 #define CLK_TOP_AUD_1_SEL 125 macro
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| H A D | mt8192-clk.h | 59 #define CLK_TOP_AUD_1_SEL 47 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 446 MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15),
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| H A D | clk-mt8512.c | 515 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
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