Searched refs:CLK_TOP_APLL_SEL (Results 1 - 12 of 12) sorted by relevance

/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8135-clk.h102 #define CLK_TOP_APLL_SEL 91 macro
H A Dmt2701-clk.h107 #define CLK_TOP_APLL_SEL 96 macro
H A Dmt2712-clk.h170 #define CLK_TOP_APLL_SEL 139 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h123 #define CLK_TOP_APLL_SEL 109 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c538 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),

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