Searched refs:CLK_TOP_APLL2_SEL (Results 1 - 11 of 11) sorted by relevance

/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7622-clk.h101 #define CLK_TOP_APLL2_SEL 88 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt7622-clk.h100 #define CLK_TOP_APLL2_SEL 88 macro
H A Dmt2712-clk.h171 #define CLK_TOP_APLL2_SEL 140 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7622.c361 MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),

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