Searched refs:CLK_TOP_APLL2_DIV0 (Results 1 - 2 of 2) sorted by relevance
| /u-boot/dts/upstream/include/dt-bindings/clock/ | ||
| H A D | mediatek,mt6795-clk.h | 132 #define CLK_TOP_APLL2_DIV0 121 macro |
| H A D | mt8173-clk.h | 137 #define CLK_TOP_APLL2_DIV0 127 macro |
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