Searched refs:CLK_TOP_APLL1_DIV1 (Results 1 - 2 of 2) sorted by relevance

/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h127 #define CLK_TOP_APLL1_DIV1 116 macro
H A Dmt8173-clk.h132 #define CLK_TOP_APLL1_DIV1 122 macro

Completed in 212 milliseconds