Searched refs:CLK_TOP_APLL12_CK_DIV5 (Results 1 - 20 of 20) sorted by relevance

/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/include/dt-bindings/clock/
H A Dmt8516-clk.h119 #define CLK_TOP_APLL12_CK_DIV5 95 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8516-clk.h202 #define CLK_TOP_APLL12_CK_DIV5 170 macro
H A Dmediatek,mt8365-clk.h128 #define CLK_TOP_APLL12_CK_DIV5 118 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8365.c551 GATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6),
H A Dclk-mt8516.c728 GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),

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