Searched refs:CLK_PLL_VIDEO0 (Results 1 - 25 of 27) sorted by relevance

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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun8i-r40-ccu.h46 #define CLK_PLL_VIDEO0 7 macro
H A Dsun20i-d1-ccu.h19 #define CLK_PLL_VIDEO0 9 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dsun50i-a64-ccu.h46 #define CLK_PLL_VIDEO0 7 macro

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