Searched refs:CLK_IFR_PWM5 (Results 1 - 11 of 11) sorted by relevance

/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt6765-clk.h176 #define CLK_IFR_PWM5 12 macro
H A Dmediatek,mt8365-clk.h165 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h167 #define CLK_IFR_PWM5 12 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8365.c625 GATE_IFR2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20),

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