Searched refs:CLK_HIFSYS_PCIE0 (Results 1 - 10 of 10) sorted by relevance

/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h393 #define CLK_HIFSYS_PCIE0 2 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt2701-clk.h410 #define CLK_HIFSYS_PCIE0 3 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c728 GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),

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