/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 164 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 171 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/dts/upstream/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 160 #define CLK_APMIXED_SGMIPLL 5 macro
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H A D | mt7622-clk.h | 178 #define CLK_APMIXED_SGMIPLL 8 macro
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/u-boot/arch/arm/mach-mediatek/mt7629/ |
H A D | init.c | 38 [CLK_APMIXED_SGMIPLL] = 650000000,
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 65 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, 130 FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1), 131 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
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H A D | clk-mt7629.c | 59 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, 132 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
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