Searched refs:CLK_APMIXED_LVDSPLL (Results 1 - 14 of 14) sorted by relevance
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 115 #define CLK_APMIXED_LVDSPLL 8 macro
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| H A D | mt8167-clk.h | 18 #define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1) macro
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| H A D | mt8173-clk.h | 168 #define CLK_APMIXED_LVDSPLL 13 macro
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| H A D | mediatek,mt8365-clk.h | 239 #define CLK_APMIXED_LVDSPLL 8 macro
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| H A D | mt2712-clk.h | 18 #define CLK_APMIXED_LVDSPLL 6 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 58 PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24,
110 PLL_FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", CLK_APMIXED_LVDSPLL, 1, 2),
111 PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4),
112 PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8),
113 PLL_FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", CLK_APMIXED_LVDSPLL, 1, 16),
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 241 #define CLK_APMIXED_LVDSPLL 8 macro
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