| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 55 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
93 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
94 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
95 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
96 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
138 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
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| H A D | clk-mt7629.c | 55 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
87 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
88 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
89 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
90 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
91 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 162 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 166 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 158 #define CLK_APMIXED_ETH1PLL 3 macro
|
| H A D | mt7622-clk.h | 173 #define CLK_APMIXED_ETH1PLL 3 macro
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| /u-boot/arch/arm/mach-mediatek/mt7629/ |
| H A D | init.c | 36 [CLK_APMIXED_ETH1PLL] = 500000000,
|