/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt8512-clk.h | 193 #define CLK_APMIXED_DSPPLL 7 macro
|
H A D | mediatek,mt8365-clk.h | 242 #define CLK_APMIXED_DSPPLL 9 macro
|
/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt8365.c | 60 PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24, 129 PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), 130 PLL_FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", CLK_APMIXED_DSPPLL, 1, 2), 131 PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4), 132 PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8),
|
H A D | clk-mt8512.c | 55 PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 126 FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), 127 FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2), 128 FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4), 129 FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
|
/u-boot/dts/upstream/include/dt-bindings/clock/ |
H A D | mediatek,mt8365-clk.h | 240 #define CLK_APMIXED_DSPPLL 9 macro
|