| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8518-clk.h | 15 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8518-clk.h | 15 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8518-clk.h | 15 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8518-clk.h | 15 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8518-clk.h | 15 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 18 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8512-clk.h | 190 #define CLK_APMIXED_APLL1 4 macro
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| H A D | mt8518-clk.h | 15 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 17 #define CLK_APMIXED_APLL1 4 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 54 PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
119 PLL_FACTOR(CLK_TOP_APLL1, "apll1_ck", CLK_APMIXED_APLL1, 1, 1),
120 PLL_FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", CLK_APMIXED_APLL1, 1, 2),
121 PLL_FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", CLK_APMIXED_APLL1, 1, 4),
122 PLL_FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", CLK_APMIXED_APLL1, 1, 8),
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| H A D | clk-mt8512.c | 49 PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
110 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
111 FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
112 FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
113 FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
114 FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
115 FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
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