Searched refs:CK_TOP_PCIE_PHY_SEL (Results 1 - 9 of 9) sorted by relevance

/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7986-clk.h135 #define CK_TOP_PCIE_PHY_SEL 81 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7986.c277 TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,

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