Searched refs:CK_TOP_NET1_D8_D4 (Results 1 - 25 of 27) sorted by relevance

12

/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
H A Dmt7988-clk.h194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
H A Dmt7988-clk.h194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
H A Dmt7988-clk.h194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
H A Dmt7988-clk.h194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
H A Dmt7988-clk.h194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
/u-boot/include/dt-bindings/clock/
H A Dmt7986-clk.h74 #define CK_TOP_NET1_D8_D4 20 macro
H A Dmt7981-clk.h80 #define CK_TOP_NET1_D8_D4 26 macro
H A Dmt7988-clk.h194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7981.c75 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
142 CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
146 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
152 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
162 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
190 CK_TOP_NET1_D8_D4 };
H A Dclk-mt7986.c69 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
140 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
184 static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
H A Dclk-mt7988.c76 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
181 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
186 CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
190 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
198 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
220 CK_TOP_NET1_D8_D4 };

Completed in 226 milliseconds

12