/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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H A D | mt7988-clk.h | 194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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H A D | mt7988-clk.h | 194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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H A D | mt7988-clk.h | 194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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H A D | mt7988-clk.h | 194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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H A D | mt7988-clk.h | 194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 74 #define CK_TOP_NET1_D8_D4 20 macro
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H A D | mt7981-clk.h | 80 #define CK_TOP_NET1_D8_D4 26 macro
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H A D | mt7988-clk.h | 194 #define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7981.c | 75 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), 142 CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; 146 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, 152 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; 162 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; 190 CK_TOP_NET1_D8_D4 };
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H A D | clk-mt7986.c | 69 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), 140 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; 184 static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
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H A D | clk-mt7988.c | 76 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), 181 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; 186 CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; 190 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, 198 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; 220 CK_TOP_NET1_D8_D4 };
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