/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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H A D | mt7988-clk.h | 193 #define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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H A D | mt7988-clk.h | 193 #define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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H A D | mt7988-clk.h | 193 #define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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H A D | mt7988-clk.h | 193 #define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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H A D | mt7988-clk.h | 193 #define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 73 #define CK_TOP_NET1_D8_D2 19 macro
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H A D | mt7981-clk.h | 79 #define CK_TOP_NET1_D8_D2 25 macro
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H A D | mt7988-clk.h | 193 #define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7986.c | 68 PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), 118 CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2, 129 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2, 136 static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, 155 static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
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H A D | clk-mt7981.c | 74 PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), 140 CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, 150 CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, 157 static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, 170 CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, 182 static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
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H A D | clk-mt7988.c | 75 PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), 165 CK_TOP_NET1_D8_D2 }; 175 CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2 179 CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, 184 CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, 193 static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
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