Searched refs:CK_TOP_NET1_D5_D2 (Results 1 - 25 of 27) sorted by relevance

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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/include/dt-bindings/clock/
H A Dmt7986-clk.h71 #define CK_TOP_NET1_D5_D2 17 macro
H A Dmt7981-clk.h76 #define CK_TOP_NET1_D5_D2 22 macro
H A Dmt7988-clk.h190 #define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7986.c66 PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
147 CK_TOP_NET1_D5_D2 };

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