/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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H A D | mt7988-clk.h | 179 #define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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H A D | mt7988-clk.h | 179 #define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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H A D | mt7988-clk.h | 179 #define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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H A D | mt7988-clk.h | 179 #define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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H A D | mt7988-clk.h | 179 #define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 59 #define CK_TOP_M_D8_D2 5 macro
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H A D | mt7981-clk.h | 61 #define CK_TOP_M_D8_D2 7 macro
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H A D | mt7988-clk.h | 179 #define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7986.c | 53 PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), 134 CK_TOP_M_D8_D2 }; 151 static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; 194 CK_TOP_M_D8_D2 }; 197 CK_TOP_M_D8_D2 };
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H A D | clk-mt7981.c | 55 PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), 155 CK_TOP_M_D8_D2 }; 159 CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; 177 static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; 219 CK_TOP_M_D8_D2 }; 222 CK_TOP_M_D8_D2 }; 224 static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
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H A D | clk-mt7988.c | 60 PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), 168 CK_TOP_M_D8_D2 }; 195 CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; 205 CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; 215 CK_TOP_M_D8_D2 }; 217 static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
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