Searched refs:CK_TOP_CB_NET1_D5 (Results 1 - 25 of 27) sorted by relevance

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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
H A Dmt7988-clk.h189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
H A Dmt7988-clk.h189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
H A Dmt7988-clk.h189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
H A Dmt7988-clk.h189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
H A Dmt7988-clk.h189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
/u-boot/include/dt-bindings/clock/
H A Dmt7986-clk.h70 #define CK_TOP_CB_NET1_D5 16 macro
H A Dmt7981-clk.h75 #define CK_TOP_CB_NET1_D5 21 macro
H A Dmt7988-clk.h189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7986.c65 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
169 CK_TOP_CB_NET1_D5 };
174 CK_TOP_CB_NET1_D5 };
H A Dclk-mt7988.c71 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
142 CK_TOP_CB_NET1_D5,
150 CK_TOP_CB_NET1_D5 };
156 CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
161 CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
235 static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
H A Dclk-mt7981.c70 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
195 CK_TOP_CB_NET1_D5 };
198 CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
210 static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,

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