/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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H A D | mt7988-clk.h | 189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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H A D | mt7988-clk.h | 189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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H A D | mt7988-clk.h | 189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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H A D | mt7988-clk.h | 189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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H A D | mt7988-clk.h | 189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 70 #define CK_TOP_CB_NET1_D5 16 macro
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H A D | mt7981-clk.h | 75 #define CK_TOP_CB_NET1_D5 21 macro
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H A D | mt7988-clk.h | 189 #define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7986.c | 65 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), 169 CK_TOP_CB_NET1_D5 }; 174 CK_TOP_CB_NET1_D5 };
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H A D | clk-mt7988.c | 71 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), 142 CK_TOP_CB_NET1_D5, 150 CK_TOP_CB_NET1_D5 }; 156 CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M 161 CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5 235 static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
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H A D | clk-mt7981.c | 70 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), 195 CK_TOP_CB_NET1_D5 }; 198 CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, 210 static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
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