| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 58 #define CK_TOP_CB_M_D8 4 macro
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| H A D | mt7981-clk.h | 60 #define CK_TOP_CB_M_D8 6 macro
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| H A D | mt7988-clk.h | 178 #define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7986.c | 52 PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
120 CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
125 CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
133 static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
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| H A D | clk-mt7981.c | 54 PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
142 CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
147 CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
154 static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
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