Searched refs:CK_TOP_APLL2_D4 (Results 1 - 18 of 18) sorted by relevance

/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7986-clk.h68 #define CK_TOP_APLL2_D4 14 macro
H A Dmt7981-clk.h72 #define CK_TOP_APLL2_D4 18 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7986.c63 PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
186 static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
196 static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
H A Dclk-mt7981.c67 PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
216 static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
221 static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,

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