/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/include/dt-bindings/clock/ |
H A D | mt7986-clk.h | 216 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7981-clk.h | 237 #define CK_APMIXED_WEDMCUPLL 4 macro
|
H A D | mt7988-clk.h | 322 #define CK_APMIXED_WEDMCUPLL 6 macro
|
/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7986.c | 36 FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), 76 CK_APMIXED_WEDMCUPLL, 1, 1), 77 PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
|