Searched refs:CFG_SYS_PCIE1_IO_PHYS (Results 1 - 21 of 21) sorted by relevance

/u-boot/include/configs/
H A DMPC8548CDS.h262 #define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull macro
264 #define CFG_SYS_PCIE1_IO_PHYS 0xe3000000 macro
H A DMPC837XERDB.h172 #define CFG_SYS_PCIE1_IO_PHYS 0xB8000000 macro
H A Dp1_p2_rdb_pc.h356 #define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull macro
358 #define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 macro
H A DP1010RDB.h78 #define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull macro
80 #define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 macro
H A DP2041RDB.h225 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
H A Dkmcent2.h337 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
H A DT208xRDB.h293 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
H A DT102xRDB.h326 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
H A DT104xRDB.h280 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
H A DT4240RDB.h103 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
H A DT208xQDS.h332 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull macro
/u-boot/board/freescale/mpc8548cds/
H A Dtlb.c81 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dtlb.c53 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/p1010rdb/
H A Dtlb.c60 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/common/p_corenet/
H A Dtlb.c110 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/t102xrdb/
H A Dtlb.c62 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/t104xrdb/
H A Dtlb.c75 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/keymile/kmcent2/
H A Dtlb.c54 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/t208xqds/
H A Dtlb.c90 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/t208xrdb/
H A Dtlb.c90 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
/u-boot/board/freescale/t4rdb/
H A Dtlb.c71 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,

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