Searched refs:BR0 (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h15 #define BR0 0x5000 /* Register offset to immr */ macro
/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S127 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
140 * we configure BR0 with the same boot ROM link address).
1152 /* Initialize the BR0 with the boot ROM starting address. */
1153 lwz r4, BR0(r3)
1159 stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */

Completed in 43 milliseconds