/seL4-test-master/projects/util_libs/libplatsupport/src/plat/pc99/acpi/ |
H A D | regions.h | 30 int parent; member in struct:Region 70 Region_t new_region(region_type_t type, void *start, size_t size, int parent) argument 76 r.parent = parent; 83 void* start, size_t size, int parent) 85 return add_region(region_list, new_region(type, start, size, parent)); 90 void* start, const void* end, int parent) 92 return add_region(region_list, new_region(type, start, end - start, parent)); 82 add_region_size(RegionList_t* region_list, region_type_t type, void* start, size_t size, int parent) argument 89 add_region_range(RegionList_t* region_list, region_type_t type, void* start, const void* end, int parent) argument
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H A D | acpi.c | 90 int parent, int force_ptr) 96 dst->parent = parent; 109 * "parent" is the index of the parent table (index into dlist) 113 int table_index, int parent) 118 ZF_LOGD("ti %d, pi %d\n", table_index, parent); 129 index = create_copy_region(src, dlist, parent, 1); 180 if (slist->regions[i].parent == table_index) { 193 dst->parent 89 create_copy_region(const Region_t* src, RegionList_t* dlist, int parent, int force_ptr) argument 112 _acpi_copy_tables(const RegionList_t* slist, RegionList_t* dlist, int table_index, int parent) argument [all...] |
H A D | browser.c | 228 _browse_regions(const RegionList_t* rlist, int parent) argument 237 /* print table at region "parent" */ 238 if (parent != NOPARENT) { 239 acpi_print_table(rlist->regions[parent].start); 250 if (r->parent == parent) {
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/seL4-test-master/projects/musllibc/src/thread/ |
H A D | pthread_atfork.c | 6 void (*parent)(void); member in struct:atfork_funcs 25 if (!who && p->parent) p->parent(); 33 int pthread_atfork(void (*prepare)(void), void (*parent)(void), void (*child)(void)) argument 42 new->parent = parent;
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/seL4-test-master/projects/util_libs/libplatsupport/src/arch/arm/ |
H A D | clock.c | 154 void clk_register_child(clk_t *parent, clk_t *child) argument 158 if (child->parent != NULL) { 159 /* If we are registered with a parent */ 160 clk_t *sibling = parent->child; 161 /* Make sure that we are a sibling of the parent's child */ 167 if (child->parent == NULL) { 168 child->parent = parent; 169 child->sibling = parent->child; 170 parent [all...] |
H A D | clock.h | 25 .parent = NULL, \
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/seL4-test-master/kernel/tools/hardware/ |
H A D | device.py | 21 def __init__(self, node: pyfdt.pyfdt.FdtNode, parent: 'WrappedNode', path: str): 23 self.parent = parent 33 if parent is not None: 34 parent.add_child(self) 35 self.depth = parent.depth + 1 36 self.is_cpu_addressable: bool = parent.is_cpu_addressable and \ 61 ''' Return this node's interrupt parent's phandle ''' 62 if 'interrupt-parent' not in self.props: 63 return self.parent [all...] |
H A D | fdt.py | 31 # for easier parent lookups 40 parent = self.by_path[parent_path] 41 wrapped = WrappedNode(node, parent, name)
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/seL4-test-master/projects/util_libs/libplatsupport/src/plat/imx6/ |
H A D | clock.c | 201 fin = clk_get_freq(clk->parent); 213 fin = clk_get_freq(clk->parent); 239 clk_t* parent; local 240 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER); 241 clk_register_child(parent, clk); 257 fin = clk_get_freq(clk->parent); 282 fin = clk_get_freq(clk->parent); 319 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER); local 320 clk_register_child(parent, clk); 340 p = clk_get_freq(clk->parent); 372 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER); local 406 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_PLL2); local 438 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MMDC_CH0); local 470 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_AHB); local 520 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER); local 603 clk_t* parent; local [all...] |
H A D | i2c.c | 136 if (clk->parent == NULL) { 137 clk_t* parent = clk_get_clock(clk->clk_sys, CLK_PERCLK); local 138 assert(parent != NULL); 139 clk_register_child(parent, clk); 149 freq_t fin = clk_get_freq(clk->parent); 158 freq_t fin = clk_get_freq(clk->parent);
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/seL4-test-master/projects/util_libs/libplatsupport/src/mach/exynos/clock/ |
H A D | exynos_common_clock.c | 29 return clk_get_freq(clk->parent); 35 return exynos_pll_calc_freq((uint64_t)clk_get_freq(clk->parent), p, m, s);
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H A D | exynos_5422_clock.c | 26 return exynos_pll_calc_freq((uint64_t)clk_get_freq(clk->parent), p, m, s);
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/seL4-test-master/projects/util_libs/libplatsupport/src/mach/exynos/ |
H A D | clock.c | 28 fin = clk_get_freq(clk->parent); 42 fin = clk_get_freq(clk->parent); 45 fin = clk_set_freq(clk->parent, hz * (MASK(DIV_VAL_BITS) / 2 + 1)); 49 fin = clk_set_freq(clk->parent, hz * (MASK(DIV_VAL_BITS) / 2 + 1)); 143 clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER); local 144 clk_init(parent); 145 clk_register_child(parent, clk);
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/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos4/ |
H A D | clock.c | 159 clk_t* parent; local 162 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MOUTAPLL); 166 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MUXCORE); 169 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DIVCORE); 175 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DIVCORE2); 178 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_ATCLK); 181 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_DIVCOPY); 184 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MUXHPM); 188 parent = NULL; 190 assert(parent); 234 clk_t* parent = NULL; local [all...] |
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos5/ |
H A D | clock.c | 162 fin = clk_get_freq(clk->parent); 192 fin = clk_get_freq(clk->parent); 210 clk_t* parent; local 217 parent = clk_get_clock(clk->clk_sys, clk_src_peri_blk[src]); 218 assert(parent); 219 clk_init(parent); 220 clk_register_child(parent, clk); 240 fin = clk_get_freq(clk->parent); 250 fin = clk_get_freq(clk->parent); 269 clk_t* parent; local [all...] |
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/zynq7000/ |
H A D | clock.c | 462 fin = clk_get_freq(clk->parent); 478 fin = clk_get_freq(clk->parent); 518 clk_t* parent; local 519 parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER); 520 clk_register_child(parent, clk); 591 fin = clk_get_freq(clk->parent); 611 fin = clk_get_freq(clk->parent); 631 clk_t* parent; local 634 parent = clk_get_clock(clk_get_clock_sys(clk), parent_id); 635 clk_register_child(parent, cl 721 clk_t* parent; local 862 clk_t* parent; local 939 clk_t* parent; local [all...] |
/seL4-test-master/projects/seL4_libs/libsel4utils/include/sel4utils/ |
H A D | thread.h | 69 * @param parent vspace structure of the thread calling this function, used for temporary mappings 79 int sel4utils_configure_thread(vka_t *vka, vspace_t *parent, vspace_t *alloc, seL4_CPtr fault_endpoint, 86 int sel4utils_configure_thread_config(vka_t *vka, vspace_t *parent, vspace_t *alloc,
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/seL4-test-master/projects/musllibc/src/search/ |
H A D | tsearch_avl.c | 123 int (*cmp)(const void *, const void *), struct node *parent) 140 return parent; 143 parent = remove(&(*n)->left, k, cmp, *n); 145 parent = remove(&(*n)->right, k, cmp, *n); 146 if (parent) 148 return parent; 122 remove(struct node **n, const void *k, int (*cmp)(const void *, const void *), struct node *parent) argument
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/seL4-test-master/kernel/manual/tools/ |
H A D | parse_doxygen_xml.py | 129 def parse_brief(self, parent): 133 para_nodes = parent.find('briefdescription').find_all('para') 136 def parse_detailed_desc(self, parent, ref_dict): 143 types_iter = iter(parent.find_all('type')) 144 names = parent.find_all('declname') 157 param_items = parent.find_all("parameteritem") 176 for n in parent.detaileddescription.find_all('para', recursive=False): 183 simplesects = parent.find_all("simplesect") 190 def parse_prototype(self, parent, escape=True): 195 inline = parent["inlin [all...] |
/seL4-test-master/projects/util_libs/libplatsupport/arch_include/arm/platsupport/ |
H A D | clock.h | 55 clk_t *parent; member in struct:clock 56 /// Provide linked list for this clock's parent. 180 * If the parent clock frequency ever changes, the recal function for the 182 * @param[in] parent The parent of this clock relationship 185 void clk_register_child(clk_t *parent, clk_t *child);
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/seL4-test-master/projects/seL4_libs/libsel4allocman/include/allocman/utspace/ |
H A D | split.h | 26 /* if this is a child node, represents our parent. Our parent must by 28 struct utspace_split_node *parent; member in struct:utspace_split_node 29 /* if we have a parent, then this is a pointer to our other sibling */
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/seL4-test-master/tools/riscv-pk/machine/ |
H A D | finisher.c | 37 fdt_get_address(prop->node->parent, prop->value, &scan->reg);
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H A D | uart.c | 51 fdt_get_address(prop->node->parent, prop->value, &scan->reg);
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H A D | uart16550.c | 45 fdt_get_address(prop->node->parent, prop->value, &scan->reg);
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/seL4-test-master/projects/seL4_libs/libsel4allocman/src/utspace/ |
H A D | split.c | 82 node->parent = NULL; 205 /* all is done. remove the parent and insert the children */ 207 left->parent = right->parent = node; 331 struct utspace_split_node *parent = node->parent; local 333 if (parent && !node->sibling->head) { 339 /* put the parent back in */ 340 _utspace_split_free(alloc, split, (seL4_Word) parent, size_bits + 1);
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