Searched refs:instruction (Results 1 - 12 of 12) sorted by relevance
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/pc99/platsupport/plat/acpi/tables/ |
H A D | erst.h | 17 uint8_t instruction; member in struct:acpi_erst_entry
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/seL4-test-master/kernel/src/arch/arm/armv/armv8-a/64/ |
H A D | cache.c | 37 static inline word_t readCacheSize(int level, bool_t instruction) argument 43 MSR("csselr_el1", ((level << 1) | instruction));
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/seL4-test-master/kernel/src/arch/arm/armv/armv8-a/32/ |
H A D | cache.c | 41 static inline word_t readCacheSize(int level, bool_t instruction) argument 47 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | instruction));
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/seL4-test-master/kernel/src/arch/arm/armv/armv7-a/ |
H A D | cache.c | 41 static inline word_t readCacheSize(int level, bool_t instruction) argument 47 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | instruction));
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/seL4-test-master/projects/sel4_projects_libs/libsel4vm/src/arch/arm/ |
H A D | fault.c | 61 static inline int thumb_is_32bit_instruction(seL4_Word instruction) argument 63 switch ((instruction >> 11) & 0x1f) { 77 /* Fetch the instruction */ 81 /* Fixup the instruction */ 87 /* Swap half words for a 32 bit instruction */ 90 /* Mask instruction for 16 bit instruction */ 97 f->instruction = inst; 108 inst = f->instruction; 154 inst = f->instruction; [all...] |
H A D | fault.h | 48 /// The IPA of the instruction which caused the fault 58 /// If the instruction requires fetching, cache it here 59 seL4_Word instruction; member in struct:fault 138 * Emulates the faulting instruction of the VM on the provided data. 252 * Determine if a fault was caused by a 32 bit instruction 254 * @return 0 if it is a 16 bit instruction, otherwise, it is 32bit
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/seL4-test-master/projects/util_libs/libplatsupport/src/arch/arm/ |
H A D | dma330.c | 74 /* DMAC instruction set */ 110 /* DMAC instruction sizes */ 407 printf("Undefined instruction. "); 459 dmac_exec(dma330_t dma330, uint64_t instruction, int channel) argument 463 inst1 = instruction >> 16; 464 inst0 = instruction << 16;
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/seL4-test-master/kernel/src/arch/x86/32/ |
H A D | traps.S | 464 movl (4 * NextIP)(%esp), %ebx # EBX contains EIP of the exception generating instruction 515 # EDX : user EIP (pointing to the sysenter instruction)
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/seL4-test-master/kernel/src/arch/x86/64/ |
H A D | traps.S | 84 * lea where possible as it has a more efficient instruction representation 586 # r11, the instruction *AFTER* the syscall is in 628 # RDX : user EIP (pointing to the sysenter instruction)
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/seL4-test-master/kernel/manual/parts/ |
H A D | threads.tex | 46 \apifunc{seL4\_TCB\_WriteRegisters}{tcb_writeregisters} with an initial stack pointer and instruction 434 Breakpoints, watchpoints, trace-events and instruction-performance sampling 455 Cortex A7 for example, there are 6 exclusive instruction breakpoint registers, 458 The instruction breakpoint registers will always be assigned the lower API-IDs, 467 capable of generating a fault \textbf{only} on instruction execution. Currently this will be 469 in \texttt{seL4\_FirstBreakpoint}. If there are no instruction-break exclusive 482 supports both instruction and data breaks. Currently this will be set only on 495 \reg{Breakpoint instruction address} & \ipcbloc{IPCBuffer[0]} \\ 514 an instruction breakpoint, to use when setting up the single-stepping 547 \reg{Breakpoint instruction addres [all...] |
H A D | api.tex | 58 that the breakpoint should occur on instruction execution at the specified 86 breakpoint, whether instruction execution, or data access;
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H A D | io.tex | 140 appropriate action and restart the thread at the faulting instruction.
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