Searched refs:L2 (Results 1 - 4 of 4) sorted by relevance

/seL4-test-master/projects/musllibc/src/math/
H A Dpow.c71 L2 = 4.28571428578550184252e-01, /* 0x3FDB6DB6, 0xDB6FABFF */ variable
255 r = s2*s2*(L1+s2*(L2+s2*(L3+s2*(L4+s2*(L5+s2*L6)))));
H A Dpowf.c27 L2 = 4.2857143283e-01, /* 0x3edb6db7 */ variable
183 r = s2*s2*(L1+s2*(L2+s2*(L3+s2*(L4+s2*(L5+s2*L6)))));
/seL4-test-master/kernel/src/arch/arm/machine/
H A Dl2c_310.c222 #error L2CC_L2C310_PPTR must be defined for virtual memory access to the L2 cache controller
251 /* L2 cache must be disabled during initialisation */
332 /* 6: Enable the L2 cache */
/seL4-test-master/kernel/manual/parts/
H A Dcspace.tex435 an 8-bit radix. The second CNode is reached via the L2 CNode Cap.
450 \item[L2 CNode Cap.] Recall that to address a \obj{CNode} capability,
453 translated. L2 CNode Cap resides at offset 0x0F of the first CNode,
458 second CNode, which is reached by the L2 CNode Cap. The second CNode
461 the L2 and L3 CNode Caps are the same, but that their depth limits

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