Searched refs:CLK_UART1 (Results 1 - 8 of 8) sorted by relevance

/seL4-test-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/
H A Dclock.h40 CLK_UART1, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/
H A Dclock.h23 CLK_UART1, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/zynq7000/platsupport/plat/
H A Dclock.h41 CLK_UART1, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos4/
H A Dclock.c372 [CLK_UART1] = &uart1_clk,
402 [CLK_UART1] = 0 * MHZ,
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dclock.c373 [CLK_UART1 ] = &uart1_clk,
400 [CLK_UART1 ] = 64 * MHZ,
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c760 case CLK_UART1:
821 case CLK_UART1:
1026 [CLK_UART1] = &uart1_clk,
1058 [CLK_UART1] = 25 * MHZ,
/seL4-test-master/projects/sel4_projects_libs/libsel4vmmplatsupport/src/plat/exynos5/devices/
H A Dvclock.c198 [CLK_UART1 ] = CLK_DEFN(uart1_data),
/seL4-test-master/projects/util_libs/libplatsupport/src/mach/exynos/
H A Dserial.c123 [PS_SERIAL1] = CLK_UART1,

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