Searched refs:CLK_UART1 (Results 1 - 8 of 8) sorted by relevance
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/ |
H A D | clock.h | 40 CLK_UART1, enumerator in enum:clk_id
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/seL4-test-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/ |
H A D | clock.h | 23 CLK_UART1, enumerator in enum:clk_id
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/seL4-test-master/projects/util_libs/libplatsupport/plat_include/zynq7000/platsupport/plat/ |
H A D | clock.h | 41 CLK_UART1, enumerator in enum:clk_id
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/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos4/ |
H A D | clock.c | 372 [CLK_UART1] = &uart1_clk, 402 [CLK_UART1] = 0 * MHZ,
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/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos5/ |
H A D | clock.c | 373 [CLK_UART1 ] = &uart1_clk, 400 [CLK_UART1 ] = 64 * MHZ,
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/seL4-test-master/projects/util_libs/libplatsupport/src/plat/zynq7000/ |
H A D | clock.c | 760 case CLK_UART1: 821 case CLK_UART1: 1026 [CLK_UART1] = &uart1_clk, 1058 [CLK_UART1] = 25 * MHZ,
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/seL4-test-master/projects/sel4_projects_libs/libsel4vmmplatsupport/src/plat/exynos5/devices/ |
H A D | vclock.c | 198 [CLK_UART1 ] = CLK_DEFN(uart1_data),
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/seL4-test-master/projects/util_libs/libplatsupport/src/mach/exynos/ |
H A D | serial.c | 123 [PS_SERIAL1] = CLK_UART1,
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