Searched refs:CLK_SPI0 (Results 1 - 8 of 8) sorted by relevance

/seL4-test-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/
H A Dclock.h44 CLK_SPI0, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/
H A Dclock.h17 CLK_SPI0, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/zynq7000/platsupport/plat/
H A Dclock.h36 CLK_SPI0, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dclock.c148 case CLK_SPI0:
180 case CLK_SPI0:
367 [CLK_SPI0 ] = &spi0_clk,
408 [CLK_SPI0 ] = 6 * MHZ,
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/exynos4/
H A Dclock.c375 [CLK_SPI0] = &spi0_clk,
411 [CLK_SPI0] = 0 * MHZ,
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c764 case CLK_SPI0:
825 case CLK_SPI0:
1027 [CLK_SPI0] = &spi0_clk,
1059 [CLK_SPI0] = 200 * MHZ,
/seL4-test-master/projects/util_libs/libplatsupport/src/mach/exynos/
H A Dspi.c144 { .regs = NULL, .mux = MUX_SPI0, .clkid = CLK_SPI0 },
/seL4-test-master/projects/sel4_projects_libs/libsel4vmmplatsupport/src/plat/exynos5/devices/
H A Dvclock.c192 [CLK_SPI0 ] = CLK_DEFN(spi0_data),

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