Searched refs:CLK_GATE_PCIERX0 (Results 1 - 2 of 2) sorted by relevance

/seL4-test-master/projects/util_libs/libplatsupport/plat_include/tk1/platsupport/plat/
H A Dclock_indexes.h321 CLK_GATE_PCIERX0, /* Enabled on reset, CLK_GATE_PCIE is master */ enumerator in enum:clock_gate
/seL4-test-master/projects/util_libs/libplatsupport/plat_include/tx2/platsupport/plat/
H A Dclock.h305 CLK_GATE_PCIERX0, enumerator in enum:clock_gate

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