Searched refs:CLK_FPGA_PL0 (Results 1 - 2 of 2) sorted by relevance

/seL4-test-master/projects/util_libs/libplatsupport/plat_include/zynq7000/platsupport/plat/
H A Dclock.h45 CLK_FPGA_PL0, enumerator in enum:clk_id
/seL4-test-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c888 case CLK_FPGA_PL0:
1033 [CLK_FPGA_PL0] = &fpga_pl0_clk,
1065 [CLK_FPGA_PL0] = 50 * MHZ,

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