Searched refs:vaddr (Results 1 - 25 of 248) sorted by relevance

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/seL4-refos-master/libs/libplatsupport/mach_include/zynq/platsupport/mach/
H A Daxi_uartlite.h13 int axi_uartlite_init(void* vaddr, ps_chardevice_t *dev);
/seL4-refos-master/projects/util_libs/libplatsupport/mach_include/zynq/platsupport/mach/
H A Daxi_uartlite.h13 int axi_uartlite_init(void* vaddr, ps_chardevice_t *dev);
/seL4-refos-master/libs/libplatsupport/src/plat/fvp/
H A Dserial.c35 if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) {
36 ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK;
43 while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0);
45 *REG_PTR(d->vaddr, UARTDR) = c;
56 *REG_PTR(dev->vaddr, UARTICR) = 0x7f0;
64 void* vaddr = chardev_map(defn, ops); local
65 if (vaddr == NULL) {
71 dev->vaddr = (void*)vaddr;
79 *REG_PTR(dev->vaddr, UARTIMS
[all...]
/seL4-refos-master/libs/libplatsupport/src/plat/hikey/
H A Dserial.c32 if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) {
33 ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK;
40 while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0);
42 *REG_PTR(d->vaddr, UARTDR) = c;
53 *REG_PTR(dev->vaddr, UARTICR) = 0x7f0;
61 void* vaddr = chardev_map(defn, ops); local
62 if (vaddr == NULL) {
68 dev->vaddr = (void*)vaddr;
76 *REG_PTR(dev->vaddr, UARTIMS
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/fvp/
H A Dserial.c35 if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) {
36 ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK;
43 while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0);
45 *REG_PTR(d->vaddr, UARTDR) = c;
56 *REG_PTR(dev->vaddr, UARTICR) = 0x7f0;
64 void* vaddr = chardev_map(defn, ops); local
65 if (vaddr == NULL) {
71 dev->vaddr = (void*)vaddr;
79 *REG_PTR(dev->vaddr, UARTIMS
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/hikey/
H A Dserial.c32 if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) {
33 ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK;
40 while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0);
42 *REG_PTR(d->vaddr, UARTDR) = c;
53 *REG_PTR(dev->vaddr, UARTICR) = 0x7f0;
61 void* vaddr = chardev_map(defn, ops); local
62 if (vaddr == NULL) {
68 dev->vaddr = (void*)vaddr;
76 *REG_PTR(dev->vaddr, UARTIMS
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/qemu-arm-virt/
H A Dserial.c35 if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) {
36 ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK;
43 while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0);
45 *REG_PTR(d->vaddr, UARTDR) = c;
55 *REG_PTR(dev->vaddr, UARTICR) = 0x7f0;
63 void *vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
70 dev->vaddr = (void *)vaddr;
78 *REG_PTR(dev->vaddr, UARTIMS
[all...]
/seL4-refos-master/libs/libplatsupport/src/plat/qemu-arm-virt/
H A Dserial.c35 if ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_RXFE) == 0) {
36 ch = *REG_PTR(d->vaddr, UARTDR) & RHR_MASK;
43 while ((*REG_PTR(d->vaddr, UARTFR) & PL011_UARTFR_TXFF) != 0);
45 *REG_PTR(d->vaddr, UARTDR) = c;
55 *REG_PTR(dev->vaddr, UARTICR) = 0x7f0;
63 void *vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
70 dev->vaddr = (void *)vaddr;
78 *REG_PTR(dev->vaddr, UARTIMS
[all...]
/seL4-refos-master/kernel/src/arch/arm/armv/armv7-a/
H A Dtlb.c11 void lockTLBEntry(vptr_t vaddr) argument
18 void lockTLBEntry(vptr_t vaddr) argument
49 lockTLBEntryCritical(vaddr, x, y);
/seL4-refos-master/libs/libplatsupport/src/plat/am335x/
H A Dserial.c33 if (*REG_PTR(d->vaddr, LSR) & LSR_RXFIFOE) {
34 ch = *REG_PTR(d->vaddr, RHR) & RHR_MASK;
41 while (!(*REG_PTR(d->vaddr, LSR) & LSR_TXFIFOE)) {
44 *REG_PTR(d->vaddr, THR) = c;
63 void* vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
70 dev->vaddr = (void*)vaddr;
78 *REG_PTR(dev->vaddr, IER) = IER_RHRIT;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/am335x/
H A Dserial.c33 if (*REG_PTR(d->vaddr, LSR) & LSR_RXFIFOE) {
34 ch = *REG_PTR(d->vaddr, RHR) & RHR_MASK;
41 while (!(*REG_PTR(d->vaddr, LSR) & LSR_TXFIFOE)) {
44 *REG_PTR(d->vaddr, THR) = c;
63 void* vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
70 dev->vaddr = (void*)vaddr;
78 *REG_PTR(dev->vaddr, IER) = IER_RHRIT;
/seL4-refos-master/libs/libplatsupport/src/plat/rockpro64/
H A Dserial.c33 if (*REG_PTR(d->vaddr, LSR) & LSR_RXFIFOE) {
34 ch = *REG_PTR(d->vaddr, RHR) & RHR_MASK;
41 while (!(*REG_PTR(d->vaddr, LSR) & LSR_TXFIFOE)) {
44 *REG_PTR(d->vaddr, THR) = c;
63 void* vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
70 dev->vaddr = (void*)vaddr;
78 *REG_PTR(dev->vaddr, IER) = IER_RHRIT;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/rockpro64/
H A Dserial.c33 if (*REG_PTR(d->vaddr, LSR) & LSR_RXFIFOE) {
34 ch = *REG_PTR(d->vaddr, RHR) & RHR_MASK;
41 while (!(*REG_PTR(d->vaddr, LSR) & LSR_TXFIFOE)) {
44 *REG_PTR(d->vaddr, THR) = c;
63 void* vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
70 dev->vaddr = (void*)vaddr;
78 *REG_PTR(dev->vaddr, IER) = IER_RHRIT;
/seL4-refos-master/libs/libplatsupport/src/plat/bcm2837/
H A Dserial.c54 while ( !(*REG_PTR(d->vaddr, MU_LSR) & MU_LSR_TXIDLE) );
55 *REG_PTR(d->vaddr, MU_IO) = (c & 0xff);
62 while ( !(*REG_PTR(d->vaddr, MU_LSR) & MU_LSR_DATAREADY) );
63 return *REG_PTR(d->vaddr, MU_IO);
71 void* vaddr = chardev_map(defn, ops); local
73 if (vaddr == NULL) {
79 dev->vaddr = (void*)vaddr;
/seL4-refos-master/libs/libplatsupport/src/plat/omap3/
H A Dserial.c35 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_RXFIFIOE) {
36 return *REG_PTR(d->vaddr, IMXUART_RHR);
44 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_TXFIFOE) {
45 *REG_PTR(d->vaddr, IMXUART_THR) = c;
62 void* vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
68 dev->vaddr = vaddr;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/bcm2837/
H A Dserial.c54 while ( !(*REG_PTR(d->vaddr, MU_LSR) & MU_LSR_TXIDLE) );
55 *REG_PTR(d->vaddr, MU_IO) = (c & 0xff);
62 while ( !(*REG_PTR(d->vaddr, MU_LSR) & MU_LSR_DATAREADY) );
63 return *REG_PTR(d->vaddr, MU_IO);
71 void* vaddr = chardev_map(defn, ops); local
73 if (vaddr == NULL) {
79 dev->vaddr = (void*)vaddr;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/omap3/
H A Dserial.c35 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_RXFIFIOE) {
36 return *REG_PTR(d->vaddr, IMXUART_RHR);
44 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_TXFIFOE) {
45 *REG_PTR(d->vaddr, IMXUART_THR) = c;
62 void* vaddr = chardev_map(defn, ops); local
64 if (vaddr == NULL) {
68 dev->vaddr = vaddr;
/seL4-refos-master/libs/libplatsupport/include/platsupport/
H A Dpmem.h41 * @return vaddr the pmem is mapped to, NULL on failure.
45 void *vaddr = ps_io_map(&ops->io_mapper, region.base_addr, region.length, cached, flags); local
46 if (vaddr == NULL) {
49 return vaddr;
57 * @param vaddr the pmem_region is mapped to,
60 static inline void ps_pmem_unmap(ps_io_ops_t *ops, pmem_region_t region, void *vaddr) { argument
61 ps_io_unmap(&ops->io_mapper, vaddr, region.length);
/seL4-refos-master/libs/libplatsupport/src/plat/apq8064/
H A Dintc.c101 void* vaddr[4]; local
104 vaddr[0] = ps_io_map(&o->io_mapper, INTCTL0, 0x1000, 0, PS_MEM_NORMAL);
105 vaddr[1] = ps_io_map(&o->io_mapper, INTCTL2, 0x1000, 0, PS_MEM_NORMAL);
106 vaddr[2] = ps_io_map(&o->io_mapper, INTCTL3, 0x1000, 0, PS_MEM_NORMAL);
107 vaddr[3] = ps_io_map(&o->io_mapper, INTCTL4, 0x1000, 0, PS_MEM_NORMAL);
108 assert(vaddr[0]);
109 assert(vaddr[1]);
110 assert(vaddr[2]);
111 assert(vaddr[3]);
112 intctl[0] = (intctl_t*)((uintptr_t)vaddr[
[all...]
H A Dserial.c39 while (!(*UART_REG(d->vaddr, USR) & USR_TXEMP));
41 *UART_REG(d->vaddr, UNTX) = 1;
42 *UART_REG(d->vaddr, UTF) = c & 0xff;
59 void* vaddr = chardev_map(defn, ops); local
61 if (vaddr == NULL) {
67 dev->vaddr = (void*)vaddr;
/seL4-refos-master/projects/util_libs/libplatsupport/include/platsupport/
H A Dpmem.h41 * @return vaddr the pmem is mapped to, NULL on failure.
45 void *vaddr = ps_io_map(&ops->io_mapper, region.base_addr, region.length, cached, flags); local
46 if (vaddr == NULL) {
49 return vaddr;
57 * @param vaddr the pmem_region is mapped to,
60 static inline void ps_pmem_unmap(ps_io_ops_t *ops, pmem_region_t region, void *vaddr) { argument
61 ps_io_unmap(&ops->io_mapper, vaddr, region.length);
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/apq8064/
H A Dintc.c101 void* vaddr[4]; local
104 vaddr[0] = ps_io_map(&o->io_mapper, INTCTL0, 0x1000, 0, PS_MEM_NORMAL);
105 vaddr[1] = ps_io_map(&o->io_mapper, INTCTL2, 0x1000, 0, PS_MEM_NORMAL);
106 vaddr[2] = ps_io_map(&o->io_mapper, INTCTL3, 0x1000, 0, PS_MEM_NORMAL);
107 vaddr[3] = ps_io_map(&o->io_mapper, INTCTL4, 0x1000, 0, PS_MEM_NORMAL);
108 assert(vaddr[0]);
109 assert(vaddr[1]);
110 assert(vaddr[2]);
111 assert(vaddr[3]);
112 intctl[0] = (intctl_t*)((uintptr_t)vaddr[
[all...]
H A Dserial.c39 while (!(*UART_REG(d->vaddr, USR) & USR_TXEMP));
41 *UART_REG(d->vaddr, UNTX) = 1;
42 *UART_REG(d->vaddr, UTF) = c & 0xff;
59 void* vaddr = chardev_map(defn, ops); local
61 if (vaddr == NULL) {
67 dev->vaddr = (void*)vaddr;
/seL4-refos-master/libs/libplatsupport/src/plat/imx31/
H A Dserial.c44 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_RXFIFIOE) {
45 data = *REG_PTR(d->vaddr, IMXUART_RHR);
56 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_TXFIFOE) {
57 *REG_PTR(d->vaddr, IMXUART_THR) = c;
78 void* vaddr = chardev_map(defn, ops); local
80 if (vaddr == NULL) {
84 dev->vaddr = vaddr;
95 *REG_PTR(dev->vaddr, IMXUART_UCR1) |= IMXUART_LSR_RXFIFIOE;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/imx31/
H A Dserial.c44 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_RXFIFIOE) {
45 data = *REG_PTR(d->vaddr, IMXUART_RHR);
56 if (*REG_PTR(d->vaddr, IMXUART_LSR) & IMXUART_LSR_TXFIFOE) {
57 *REG_PTR(d->vaddr, IMXUART_THR) = c;
78 void* vaddr = chardev_map(defn, ops); local
80 if (vaddr == NULL) {
84 dev->vaddr = vaddr;
95 *REG_PTR(dev->vaddr, IMXUART_UCR1) |= IMXUART_LSR_RXFIFIOE;

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