Searched refs:reg (Results 1 - 25 of 136) sorted by relevance

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/seL4-refos-master/seL4_tools/elfloader-tool/include/arch-arm/armv/armv6/armv/
H A Dassembler.h15 #define PIALL(reg) p15, 0, reg, c7, c5, 4
16 #define ISB(reg) p15, 0, reg, c7, c5, 4
17 #define DCALL(reg) p15, 0, reg, c7, c10, 0
18 #define DSB(reg) p15, 0, reg, c7, c10, 4
19 #define DCIALL(reg) p15, 0, reg, c
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/seL4-refos-master/tools/elfloader/include/arch-arm/armv/armv6/armv/
H A Dassembler.h15 #define PIALL(reg) p15, 0, reg, c7, c5, 4
16 #define ISB(reg) p15, 0, reg, c7, c5, 4
17 #define DCALL(reg) p15, 0, reg, c7, c10, 0
18 #define DSB(reg) p15, 0, reg, c7, c10, 4
19 #define DCIALL(reg) p15, 0, reg, c
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/seL4-refos-master/kernel/include/arch/arm/armv/armv8-a/64/armv/
H A Dmachine.h29 #define MRS(reg, v) asm volatile("mrs %x0," reg : "=r"(v))
30 #define MSR(reg, v) \
33 asm volatile("msr " reg ",%x0" :: "r" (_v));\
36 #define SYSTEM_WRITE_WORD(reg, v) MSR(reg, v)
37 #define SYSTEM_READ_WORD(reg, v) MRS(reg, v)
38 #define SYSTEM_WRITE_64(reg, v) MSR(reg,
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H A Dvcpu.h135 word_t reg; local
136 MRS(REG_TTBR0_EL1, reg);
137 return reg;
140 static inline void writeTTBR0(word_t reg) argument
142 MSR(REG_TTBR0_EL1, reg);
147 word_t reg; local
148 MRS(REG_TTBR1_EL1, reg);
149 return reg;
152 static inline void writeTTBR1(word_t reg) argument
154 MSR(REG_TTBR1_EL1, reg);
159 word_t reg; local
164 writeTCR(word_t reg) argument
171 word_t reg; local
176 writeMAIR(word_t reg) argument
183 word_t reg; local
188 writeAMAIR(word_t reg) argument
195 uint32_t reg; local
200 writeCIDR(word_t reg) argument
207 word_t reg; local
212 writeACTLR(word_t reg) argument
219 uint32_t reg; local
224 writeAFSR0(word_t reg) argument
231 uint32_t reg; local
236 writeAFSR1(word_t reg) argument
243 uint32_t reg; local
248 writeESR(word_t reg) argument
255 word_t reg; local
260 writeFAR(word_t reg) argument
268 uint32_t reg; local
275 word_t reg; local
280 writeVBAR(word_t reg) argument
287 word_t reg; local
292 writeSP_EL1(word_t reg) argument
299 word_t reg; local
304 writeELR_EL1(word_t reg) argument
311 word_t reg; local
316 writeSPSR_EL1(word_t reg) argument
323 word_t reg; local
328 writeCPACR_EL1(word_t reg) argument
335 word_t reg; local
340 writeCNTV_TVAL_EL0(word_t reg) argument
347 word_t reg; local
352 writeCNTV_CTL_EL0(word_t reg) argument
359 word_t reg; local
364 writeCNTV_CVAL_EL0(word_t reg) argument
371 word_t reg; local
376 writeCNTVOFF_EL2(word_t reg) argument
383 word_t reg; local
388 writeCNTKCTL_EL1(word_t reg) argument
395 word_t reg; local
400 writeVMPIDR_EL2(word_t reg) argument
407 word_t reg = 0; local
466 vcpu_hw_write_reg(word_t reg_index, word_t reg) argument
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/seL4-refos-master/seL4_tools/elfloader-tool/include/arch-arm/armv/armv8-a/64/armv/
H A Dmachine.h30 #define MRS(reg, v) asm volatile("mrs %0," reg : "=r"(v))
31 #define MSR(reg, v) \
34 asm volatile("msr " reg ",%0" :: "r" (_v));\
/seL4-refos-master/tools/elfloader/include/arch-arm/armv/armv8-a/64/armv/
H A Dmachine.h30 #define MRS(reg, v) asm volatile("mrs %0," reg : "=r"(v))
31 #define MSR(reg, v) \
34 asm volatile("msr " reg ",%0" :: "r" (_v));\
/seL4-refos-master/seL4_tools/elfloader-tool/include/arch-arm/32/mode/
H A Dassembler.h13 #define SCTLR(reg) p15, 0, reg, c1, c0, 0
14 #define CLIDR(reg) p15, 1, reg, c0, c0, 1
15 #define TTBR0(reg) p15, 0, reg, c2, c0, 0
16 #define TTBCR(reg) p15, 0, reg, c2, c0, 2
17 #define DACR(reg) p15, 0, reg, c
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/seL4-refos-master/tools/elfloader/include/arch-arm/32/mode/
H A Dassembler.h13 #define SCTLR(reg) p15, 0, reg, c1, c0, 0
14 #define CLIDR(reg) p15, 1, reg, c0, c0, 1
15 #define TTBR0(reg) p15, 0, reg, c2, c0, 0
16 #define TTBCR(reg) p15, 0, reg, c2, c0, 2
17 #define DACR(reg) p15, 0, reg, c
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/seL4-refos-master/seL4_tools/elfloader-tool/include/arch-arm/armv/armv7ve/armv/
H A Dassembler.h15 #define CCSIDR(reg) p15, 1, reg, c0, c0, 0
16 #define CSSELR(reg) p15, 2, reg, c0, c0, 0
17 #define ACTLR(reg) p15, 0, reg, c1, c0, 1
18 #define DISW(reg) p15, 0, reg, c7, c6, 2
19 #define DCISW(reg) p15, 0, reg, c
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/seL4-refos-master/seL4_tools/elfloader-tool/include/arch-arm/armv/armv7-a/armv/
H A Dassembler.h15 #define CCSIDR(reg) p15, 1, reg, c0, c0, 0
16 #define CSSELR(reg) p15, 2, reg, c0, c0, 0
17 #define ACTLR(reg) p15, 0, reg, c1, c0, 1
18 #define DISW(reg) p15, 0, reg, c7, c6, 2
19 #define DCISW(reg) p15, 0, reg, c
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/seL4-refos-master/seL4_tools/elfloader-tool/include/arch-arm/armv/armv8-a/32/armv/
H A Dassembler.h15 #define CCSIDR(reg) p15, 1, reg, c0, c0, 0
16 #define CSSELR(reg) p15, 2, reg, c0, c0, 0
17 #define ACTLR(reg) p15, 0, reg, c1, c0, 1
18 #define DISW(reg) p15, 0, reg, c7, c6, 2
19 #define DCISW(reg) p15, 0, reg, c
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/seL4-refos-master/tools/elfloader/include/arch-arm/armv/armv8-a/32/armv/
H A Dassembler.h15 #define CCSIDR(reg) p15, 1, reg, c0, c0, 0
16 #define CSSELR(reg) p15, 2, reg, c0, c0, 0
17 #define ACTLR(reg) p15, 0, reg, c1, c0, 1
18 #define DISW(reg) p15, 0, reg, c7, c6, 2
19 #define DCISW(reg) p15, 0, reg, c
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/seL4-refos-master/tools/elfloader/include/arch-arm/armv/armv7ve/armv/
H A Dassembler.h15 #define CCSIDR(reg) p15, 1, reg, c0, c0, 0
16 #define CSSELR(reg) p15, 2, reg, c0, c0, 0
17 #define ACTLR(reg) p15, 0, reg, c1, c0, 1
18 #define DISW(reg) p15, 0, reg, c7, c6, 2
19 #define DCISW(reg) p15, 0, reg, c
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/seL4-refos-master/tools/elfloader/include/arch-arm/armv/armv7-a/armv/
H A Dassembler.h15 #define CCSIDR(reg) p15, 1, reg, c0, c0, 0
16 #define CSSELR(reg) p15, 2, reg, c0, c0, 0
17 #define ACTLR(reg) p15, 0, reg, c1, c0, 1
18 #define DISW(reg) p15, 0, reg, c7, c6, 2
19 #define DCISW(reg) p15, 0, reg, c
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/seL4-refos-master/kernel/include/arch/arm/arch/64/mode/
H A Dmachine_pl2.h11 static inline void writeTPIDR_EL2(word_t reg) argument
13 MSR("tpidr_el2", reg);
18 word_t reg; local
19 MRS("tpidr_el2", reg);
20 return reg;
25 static inline void writeTPIDR_EL2(word_t reg) {} argument
/seL4-refos-master/kernel/include/arch/arm/armv/armv6/armv/
H A Dmachine.h53 #define SYSTEM_WRITE_WORD(reg, v) MCR(reg, v)
54 #define SYSTEM_READ_WORD(reg, v) MRC(reg, v)
55 #define SYSTEM_WRITE_64(reg, v) MCRR(reg, v)
56 #define SYSTEM_READ_64(reg, v) MRRC(reg, v)
/seL4-refos-master/kernel/src/drivers/smmu/
H A Dsmmuv2.c180 uint32_t reg, field; local
182 reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_IDR0);
184 if (reg & IDR0_S1TS) {
187 if (reg & IDR0_S2TS) {
190 if (reg & IDR0_NTS) {
194 if (reg & IDR0_SMS) {
198 if ((reg & IDR0_ATOSNS) == 0) {
202 field = IDR0_PTFS_VAL(reg & IDR0_PTFS);
214 smmu_dev_knowledge.num_cfault_ints = IDR0_NUMIRPT_VAL(reg & IDR0_NUMIRPT);
216 if (reg
278 uint32_t reg = 0; local
380 uint32_t reg = 0; local
407 uint32_t reg = 0; local
469 uint32_t reg = 0; local
531 smmu_write_reg32(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_SCTLR, reg); local
537 uint32_t reg = smmu_read_reg32(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_SCTLR); local
539 smmu_write_reg32(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_SCTLR, reg); local
546 uint32_t reg = 0; local
563 uint32_t reg = S2CR_TYPE_SET(S2CR_TYPE_FAULT); local
590 uint32_t reg = TLBIVMID_SET(cb); local
607 uint64_t reg = CBn_TLBIIPAS2_SET(vaddr); local
608 smmu_write_reg64(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_TLBIIPAS2, reg); local
627 uint32_t reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_sGFSR); local
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/seL4-refos-master/kernel/src/arch/arm/32/
H A Dhyp_traps.S15 #define HVBAR(reg) p15, 4, reg, c12, c0, 0
16 #define HCR(reg) p15, 4, reg, c1 , c1, 0
17 #define HSCTLR(reg) p15, 4, reg, c1 , c0, 0
18 #define HACTLR(reg) p15, 4, reg, c1 , c0, 1
19 #define HDCR(reg) p15, 4, reg, c
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/seL4-refos-master/kernel/include/arch/arm/armv/armv7-a/armv/
H A Dmachine.h47 #define SYSTEM_WRITE_WORD(reg, v) MCR(reg, v)
48 #define SYSTEM_READ_WORD(reg, v) MRC(reg, v)
49 #define SYSTEM_WRITE_64(reg, v) MCRR(reg, v)
50 #define SYSTEM_READ_64(reg, v) MRRC(reg, v)
/seL4-refos-master/kernel/include/arch/arm/armv/armv8-a/32/armv/
H A Dmachine.h47 #define SYSTEM_WRITE_WORD(reg, v) MCR(reg, v)
48 #define SYSTEM_READ_WORD(reg, v) MRC(reg, v)
49 #define SYSTEM_WRITE_64(reg, v) MCRR(reg, v)
50 #define SYSTEM_READ_64(reg, v) MRRC(reg, v)
/seL4-refos-master/kernel/include/arch/arm/armv/armv7ve/armv/
H A Dmachine.h47 #define SYSTEM_WRITE_WORD(reg, v) MCR(reg, v)
48 #define SYSTEM_READ_WORD(reg, v) MRC(reg, v)
49 #define SYSTEM_WRITE_64(reg, v) MCRR(reg, v)
50 #define SYSTEM_READ_64(reg, v) MRRC(reg, v)
/seL4-refos-master/libs/libmuslc/include/sys/
H A Dreg.h7 #include <bits/reg.h>
/seL4-refos-master/projects/seL4_libs/libsel4bench/sel4_arch_include/aarch64/sel4bench/sel4_arch/
H A Dsel4bench.h17 #define PMU_WRITE(reg, v) \
20 asm volatile("msr " reg ", %0" :: "r" (_v)); \
23 #define PMU_READ(reg, v) asm volatile("mrs %0, " reg : "=r"(v))
/seL4-refos-master/projects/util_libs/libpci/src/
H A Dioreg.c55 uint32_t libpci_read_reg32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg) { argument
56 reg &= ~MASK(2);
57 libpci_out32(PCI_CONF_PORT_ADDR, 0x80000000 | bus << 16 | dev << 11 | fun << 8 | reg);
61 void libpci_write_reg32(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg, uint32_t val) { argument
62 reg &= ~MASK(2);
63 libpci_out32(PCI_CONF_PORT_ADDR, 0x80000000 | bus << 16 | dev << 11 | fun << 8 | reg);
67 uint16_t libpci_read_reg16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg) { argument
68 reg &= ~MASK(1);
69 libpci_out32(PCI_CONF_PORT_ADDR, 0x80000000 | bus << 16 | dev << 11 | fun << 8 | (reg & ~MASK(2)));
70 return ( libpci_in32(PCI_CONF_PORT_DATA) >> ((reg
73 libpci_write_reg16(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg, uint16_t val) argument
79 libpci_read_reg8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg) argument
84 libpci_write_reg8(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg, uint8_t val) argument
89 libpci_read_reg(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg, uint8_t size) argument
100 libpci_write_reg(uint8_t bus, uint8_t dev, uint8_t fun, uint8_t reg, uint32_t val, uint8_t size) argument
111 libpci_portno_reverse_lookup(uint32_t port_no, uint8_t *bus, uint8_t *dev, uint8_t *fun, uint8_t *reg) argument
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/seL4-refos-master/libs/libsel4simple-default/src/arch/arm/
H A Ddefault.c44 seL4_SlotRegion reg; local
52 reg = bi->ioSpaceCaps;
54 if (reg.end <= reg.start) {
60 *count = reg.end - reg.start;
67 seL4_SlotRegion reg; local
75 reg = bi->ioSpaceCaps;
77 if (reg.end <= reg
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