| /seL4-refos-master/libs/libplatsupport/plat_include/pc99/platsupport/plat/acpi/tables/ |
| H A D | erst.h | 17 uint8_t instruction; member in struct:acpi_erst_entry
|
| /seL4-refos-master/projects/util_libs/libplatsupport/plat_include/pc99/platsupport/plat/acpi/tables/ |
| H A D | erst.h | 17 uint8_t instruction; member in struct:acpi_erst_entry
|
| /seL4-refos-master/kernel/src/arch/arm/armv/armv8-a/64/ |
| H A D | cache.c | 37 static inline word_t readCacheSize(int level, bool_t instruction) argument
43 MSR("csselr_el1", ((level << 1) | instruction));
|
| /seL4-refos-master/projects/refos/impl/apps/process_server/src/dispatchers/ |
| H A D | fault_handler.c | 37 /*! The program counter at the faulting instruction. */
41 /*! Whether this fault was caused by a data access or an instruction. */
42 seL4_Word instruction; member in struct:procserv_vmfault_msg
59 f->instruction ? "Instruction" : "Data", f->read ? "read" : "write",
237 vmFaultNotification.arg[4] = f->instruction;
275 f->instruction ? "Instruction" : "Data", f->read ? "read" : "write",
374 vmfault.instruction = seL4_GetMR(seL4_VMFault_PrefetchFault);
|
| /seL4-refos-master/apps/process_server/src/dispatchers/ |
| H A D | fault_handler.c | 37 /*! The program counter at the faulting instruction. */
41 /*! Whether this fault was caused by a data access or an instruction. */
42 seL4_Word instruction; member in struct:procserv_vmfault_msg
59 f->instruction ? "Instruction" : "Data", f->read ? "read" : "write",
237 vmFaultNotification.arg[4] = f->instruction;
275 f->instruction ? "Instruction" : "Data", f->read ? "read" : "write",
374 vmfault.instruction = seL4_GetMR(seL4_VMFault_PrefetchFault);
|
| /seL4-refos-master/kernel/src/arch/arm/armv/armv7-a/ |
| H A D | cache.c | 41 static inline word_t readCacheSize(int level, bool_t instruction) argument
47 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | instruction));
|
| /seL4-refos-master/kernel/src/arch/arm/armv/armv8-a/32/ |
| H A D | cache.c | 41 static inline word_t readCacheSize(int level, bool_t instruction) argument
47 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | instruction));
|
| /seL4-refos-master/libs/libplatsupport/src/arch/arm/ |
| H A D | dma330.c | 74 /* DMAC instruction set */
110 /* DMAC instruction sizes */
407 printf("Undefined instruction. ");
459 dmac_exec(dma330_t dma330, uint64_t instruction, int channel) argument
463 inst1 = instruction >> 16;
464 inst0 = instruction << 16;
|
| /seL4-refos-master/projects/util_libs/libplatsupport/src/arch/arm/ |
| H A D | dma330.c | 74 /* DMAC instruction set */
110 /* DMAC instruction sizes */
407 printf("Undefined instruction. ");
459 dmac_exec(dma330_t dma330, uint64_t instruction, int channel) argument
463 inst1 = instruction >> 16;
464 inst0 = instruction << 16;
|
| /seL4-refos-master/kernel/src/arch/x86/32/ |
| H A D | traps.S | 464 movl (4 * NextIP)(%esp), %ebx # EBX contains EIP of the exception generating instruction
515 # EDX : user EIP (pointing to the sysenter instruction)
|
| /seL4-refos-master/kernel/src/arch/x86/64/ |
| H A D | traps.S | 84 * lea where possible as it has a more efficient instruction representation
586 # r11, the instruction *AFTER* the syscall is in
628 # RDX : user EIP (pointing to the sysenter instruction)
|
| /seL4-refos-master/kernel/manual/parts/ |
| H A D | threads.tex | 46 \apifunc{seL4\_TCB\_WriteRegisters}{tcb_writeregisters} with an initial stack pointer and instruction
434 Breakpoints, watchpoints, trace-events and instruction-performance sampling
455 Cortex A7 for example, there are 6 exclusive instruction breakpoint registers,
458 The instruction breakpoint registers will always be assigned the lower API-IDs,
467 capable of generating a fault \textbf{only} on instruction execution. Currently this will be
469 in \texttt{seL4\_FirstBreakpoint}. If there are no instruction-break exclusive
482 supports both instruction and data breaks. Currently this will be set only on
495 \reg{Breakpoint instruction address} & \ipcbloc{IPCBuffer[0]} \\
514 an instruction breakpoint, to use when setting up the single-stepping
547 \reg{Breakpoint instruction addres
[all...] |
| H A D | api.tex | 58 that the breakpoint should occur on instruction execution at the specified
86 breakpoint, whether instruction execution, or data access;
|
| H A D | io.tex | 140 appropriate action and restart the thread at the faulting instruction.
|