Searched refs:attributes (Results 1 - 3 of 3) sorted by relevance

/seL4-mcs-10.1.1/src/arch/arm/64/kernel/
H A Dvspace.c64 /* Stage-2 translation memory attributes */
228 map_kernel_frame(paddr_t paddr, pptr_t vaddr, vm_rights_t vm_rights, vm_attributes_t attributes) argument
232 if (vm_attributes_get_armPageCacheable(attributes)) {
328 * The memory attributes use the S2 translation values.
835 makeUser3rdLevel(paddr_t paddr, vm_rights_t vm_rights, vm_attributes_t attributes) argument
837 bool_t nonexecutable = vm_attributes_get_armExecuteNever(attributes);
839 if (vm_attributes_get_armPageCacheable(attributes)) {
882 makeUser2ndLevel(paddr_t paddr, vm_rights_t vm_rights, vm_attributes_t attributes) argument
884 bool_t nonexecutable = vm_attributes_get_armExecuteNever(attributes);
886 if (vm_attributes_get_armPageCacheable(attributes)) {
926 makeUser1stLevel(paddr_t paddr, vm_rights_t vm_rights, vm_attributes_t attributes) argument
2119 vm_attributes_t attributes; local
2245 vm_attributes_t attributes; local
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/seL4-mcs-10.1.1/manual/parts/
H A Dvspace.tex305 \caption{\label{tbl:vmattr_arm} Virtual memory attributes for ARM page
323 \caption{\label{tbl:vmattr_ia32} Virtual memory attributes for x86 page
/seL4-mcs-10.1.1/src/arch/arm/32/kernel/
H A Dvspace.c165 map_kernel_frame(paddr_t paddr, pptr_t vaddr, vm_rights_t vm_rights, vm_attributes_t attributes) argument
171 if (vm_attributes_get_armPageCacheable(attributes)) {
210 vm_attributes_get_armPageCacheable(attributes)
644 /* Setup the memory attributes: We use 2 indicies (cachable/non-cachable) */

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