Searched refs:VTCR_EL2_IRGN0 (Results 1 - 1 of 1) sorted by relevance

/seL4-mcs-10.1.1/include/arch/arm/armv/armv8-a/64/armv/
H A Dvcpu.h56 #define VTCR_EL2_IRGN0(x) ((x) << 8) macro
656 vtcr_el2 |= VTCR_EL2_IRGN0(NORMAL_WB_WA_CACHEABLE); // inner write-back, read/write allocate

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