Searched refs:CORE_IRQ_TO_IRQT (Results 1 - 17 of 17) sorted by relevance

/seL4-l4v-master/seL4/include/arch/arm/arch/machine/
H A Dgic_common.h44 #define CORE_IRQ_TO_IRQT(tgt, _irq) ((irq_t){.irq = (_irq), .target_core = (tgt)}) macro
50 CORE_IRQ_TO_IRQT((idx) / NUM_PPI, (idx) - ((idx)/NUM_PPI)*NUM_PPI): \
51 CORE_IRQ_TO_IRQT(0, (idx) - (CONFIG_MAX_NUM_NODES-1)*NUM_PPI))
54 irq_t irqInvalid = CORE_IRQ_TO_IRQT(-1, -1);
H A Dgic_v2.h166 irq = CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), active_irq[CURRENT_CPU_INDEX()] & IRQ_MASK);
H A Dgic_v3.h240 irq = CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), active_irq[CURRENT_CPU_INDEX()] & IRQ_MASK);
/seL4-l4v-master/seL4/include/machine/
H A Dinterrupt.h27 * CORE_IRQ_TO_IRQT: converts from a core id and hw irq number to an irq_t
45 #define CORE_IRQ_TO_IRQT(tgt, irq) (irq) macro
/seL4-l4v-master/seL4/src/arch/arm/kernel/
H A Dboot.c98 setIRQState(IRQInactive, CORE_IRQ_TO_IRQT(0, i));
100 setIRQState(IRQTimer, CORE_IRQ_TO_IRQT(0, KERNEL_TIMER_IRQ));
102 setIRQState(IRQReserved, CORE_IRQ_TO_IRQT(0, INTERRUPT_VGIC_MAINTENANCE));
103 setIRQState(IRQReserved, CORE_IRQ_TO_IRQT(0, INTERRUPT_VTIMER_EVENT));
106 setIRQState(IRQReserved, CORE_IRQ_TO_IRQT(0, INTERRUPT_SMMU));
111 setIRQState(IRQReserved, CORE_IRQ_TO_IRQT(0, KERNEL_PMU_IRQ));
122 setIRQState(IRQIPI, CORE_IRQ_TO_IRQT(getCurrentCPUIndex(), irq_remote_call_ipi));
123 setIRQState(IRQIPI, CORE_IRQ_TO_IRQT(getCurrentCPUIndex(), irq_reschedule_ipi));
260 maskInterrupt(true, CORE_IRQ_TO_IRQT(getCurrentCPUIndex(), i));
262 setIRQState(IRQIPI, CORE_IRQ_TO_IRQT(getCurrentCPUInde
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/seL4-l4v-master/seL4/src/drivers/timer/
H A Dgeneric_timer.c126 if (likely(isIRQActive(CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT)))) {
127 maskInterrupt(vcpu->vppi_masked[irqVPPIEventIndex(CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT))],
128 CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT));
/seL4-l4v-master/seL4/src/smp/
H A Dipi.c50 handleIPI(CORE_IRQ_TO_IRQT(getCurrentCPUIndex(), irq_remote_call_ipi), irqPath);
99 ipi_send_mask(CORE_IRQ_TO_IRQT(0, irq_remote_call_ipi), mask, true);
109 ipi_send_mask(CORE_IRQ_TO_IRQT(0, irq_reschedule_ipi), mask, false);
/seL4-l4v-master/seL4/include/smp/
H A Dlock.h78 handleIPI(CORE_IRQ_TO_IRQT(cpu, irq_remote_call_ipi), irqPath);
112 handleIPI(CORE_IRQ_TO_IRQT(cpu, irq_remote_call_ipi), irqPath);
/seL4-l4v-master/seL4/src/arch/arm/object/
H A Dinterrupt.c38 irq_t irq = (irq_t) CORE_IRQ_TO_IRQT(0, irq_w);
89 irq_t irq = CORE_IRQ_TO_IRQT(target, irq_w);
H A Dvcpu.c501 irq_t irq = (irq_t) CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), irq_w);
/seL4-l4v-master/seL4/src/object/
H A Dinterrupt.c40 irq = CORE_IRQ_TO_IRQT(0, irq_w);
/seL4-l4v-master/seL4/include/arch/arm/armv/armv8-a/64/armv/
H A Dvcpu.h636 maskInterrupt(true, CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT));
/seL4-l4v-master/seL4/include/arch/arm/armv/armv7ve/armv/
H A Dvcpu.h826 maskInterrupt(true, CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT));
/seL4-l4v-master/seL4/include/arch/arm/armv/armv7-a/armv/
H A Dvcpu.h826 maskInterrupt(true, CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT));
/seL4-l4v-master/seL4/src/machine/
H A Dcapdl.c328 irq_t irq = CORE_IRQ_TO_IRQT(target, i);
/seL4-l4v-master/seL4/include/arch/arm/armv/armv8-a/32/armv/
H A Dvcpu.h826 maskInterrupt(true, CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), INTERRUPT_VTIMER_EVENT));
/seL4-l4v-master/seL4/src/api/
H A Dsyscall.c149 ipi_send_target(CORE_IRQ_TO_IRQT(0, irq), BIT(target));

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