Searched refs:eisr0 (Results 1 - 2 of 2) sorted by relevance

/seL4-camkes-master/kernel/include/arch/arm/arch/machine/
H A Dgic_v2.h222 uint32_t eisr0; /* 0x020 RO 0x00000000 End of Interrupt Status Registers 0 and 1, see EISRn */ member in struct:gich_vcpu_ctrl_map
275 return gic_vcpu_ctrl->eisr0;
/seL4-camkes-master/kernel/src/arch/arm/object/
H A Dvcpu.c142 uint32_t eisr0, eisr1; local
156 eisr0 = get_gic_vcpu_ctrl_eisr0();
162 if (eisr0) {
163 irq_idx = ctzl(eisr0);

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