Searched refs:controller (Results 1 - 6 of 6) sorted by relevance

/seL4-camkes-master/kernel/tools/hardware/
H A Dirq.py30 ''' Get the IRQ controller's address-cells '''
36 ''' Get the IRQ controller's interrupt-cells '''
92 controller = self.tree.get_irq_controller(nexus_data.pop(0))
100 cells = controller.get_nexus_addr_cells()
101 cells += controller.get_interrupt_cells()
111 return controller.parse_irq(child, nexus_data)
198 # otherwise, just return a dummy irq controller
/seL4-camkes-master/projects/global-components/remote-drivers/picotcp-ethernet-async/camkes-include/
H A Dcamkes-picotcp-ethernet-async.h51 name##_dma.controller = VAR_STRINGIZE(client.name##_dma_pool); \
/seL4-camkes-master/tools/riscv-pk/machine/
H A Dfdt.c215 const struct fdt_scan_node *controller; member in struct:hart_scan
226 if (!scan->controller) {
238 } else if (!strcmp(prop->name, "interrupt-controller")) {
239 assert (!scan->controller);
240 scan->controller = prop->node;
260 if (scan->controller == node && scan->cpu) {
276 if (scan->controller == node) scan->controller = 0;
/seL4-camkes-master/projects/global-components/remote-drivers/picotcp-socket-sync/camkes-include/
H A Dcamkes-picotcp-socket-sync.h71 client_name##_dma.controller = VAR_STRINGIZE(client.client_name##_dma_pool);
/seL4-camkes-master/kernel/src/arch/arm/machine/
H A Dl2c_310.c222 #error L2CC_L2C310_PPTR must be defined for virtual memory access to the L2 cache controller
/seL4-camkes-master/kernel/manual/parts/
H A Dbootup.tex45 \texttt{seL4\_CapIRQControl} & global IRQ controller (see \autoref{sec:interrupts}) \\
46 \texttt{seL4\_CapASIDControl} & global ASID controller (see \autoref{ch:vspace}) \\

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