Searched refs:GPA1 (Results 1 - 4 of 4) sorted by relevance
| /seL4-camkes-master/projects/util_libs/libplatsupport/src/plat/exynos5/ |
| H A D | mux.c | 33 { .port = GPA1, .pin = 3, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
34 { .port = GPA1, .pin = 2, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
80 { .port = GPA1, .pin = 0, .value = UART_MUX_VAL},
81 { .port = GPA1, .pin = 1, .value = UART_MUX_VAL},
85 { .port = GPA1, .pin = 2, .value = UART_MUX_VAL},
86 { .port = GPA1, .pin = 3, .value = UART_MUX_VAL},
90 { .port = GPA1, .pin = 4, .value = UART_MUX_VAL},
91 { .port = GPA1, .pin = 5, .value = UART_MUX_VAL},
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| /seL4-camkes-master/projects/util_libs/libplatsupport/src/plat/exynos4/ |
| H A D | mux.c | 34 { .port = GPA1, .pin = 2, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
35 { .port = GPA1, .pin = 3, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
108 { .port = GPA1, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
109 { .port = GPA1, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
113 { .port = GPA1, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
114 { .port = GPA1, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
118 { .port = GPA1, .pin = 4, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
119 { .port = GPA1, .pin = 5, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
123 { .port = GPA1, .pin = 6, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV3X)},
124 { .port = GPA1,
[all...] |
| /seL4-camkes-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/ |
| H A D | gpio.h | 71 GPA1 = GPIOPORT(LEFT, 1), /* 0x020 */ enumerator in enum:gpio_port
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| /seL4-camkes-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/ |
| H A D | gpio.h | 71 GPA1 = GPIOPORT(LEFT, 1), /* 0x020 */ enumerator in enum:gpio_port
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