Searched refs:SEC_CTRL_PLLB_CTRL0 (Results 1 - 4 of 4) sorted by relevance

/openwrt/target/linux/oxnas/files/drivers/clk/
H A Dclk-oxnas.c111 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
118 SEC_CTRL_PLLB_CTRL0);
121 oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
133 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
/openwrt/package/boot/uboot-oxnas/files/drivers/usb/host/
H A Dehci-oxnas.c26 SEC_CTRL_PLLB_CTRL0);
/openwrt/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/
H A Dsysctl.h70 #define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0) macro
/openwrt/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/
H A Dhardware.h84 #define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0) macro

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