Searched refs:reg_val (Results 1 - 22 of 22) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c430 uint32_t reg_val, hw_index; local
437 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
438 ixgbe_log(ixgbe, "\tCTRL=%x\n", reg_val);
439 reg_val = IXGBE_READ_REG(hw, IXGBE_STATUS);
440 ixgbe_log(ixgbe, "\tSTATUS=%x\n", reg_val);
441 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
442 ixgbe_log(ixgbe, "\tCTRL_EXT=%x\n", reg_val);
443 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
444 ixgbe_log(ixgbe, "\tFCTRL=%x\n", reg_val);
449 reg_val
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H A Dixgbe_main.c2046 uint32_t reg_val; local
2090 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index));
2091 reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */
2095 reg_val |= 0x0020; /* pthresh */
2097 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index), reg_val);
2100 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2101 reg_val |= (IXGBE_RDRXCTL_CRCSTRIP | IXGBE_RDRXCTL_AGGDIS);
2102 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
2109 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) |
2111 reg_val |
2120 uint32_t reg_val; local
2284 uint32_t reg_val; local
2366 uint32_t reg_val; local
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H A Dixgbe_gld.c100 uint32_t reg_val; local
109 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
112 reg_val |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
114 reg_val &= (~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE));
116 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_FCTRL, reg_val);
H A Dixgbe_common.c461 u32 reg_val; local
473 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
474 reg_val &= ~(IXGBE_RXCTRL_RXEN);
475 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
488 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
489 if (reg_val & IXGBE_TXDCTL_ENABLE) {
490 reg_val &= ~IXGBE_TXDCTL_ENABLE;
491 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
2301 u32 reg_val; local
2314 reg_val
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/opensolaris-onvv-gate/usr/src/uts/sun4u/sys/i2c/clients/
H A Di2c_gpio.h49 uint32_t reg_val; member in struct:i2c_gpio
/opensolaris-onvv-gate/usr/src/uts/sun4u/io/i2c/clients/
H A Dadm1026.c65 * in the ioctl call. The reg_mask and reg_val members of i2c_gpio_t are
68 * that the user wants to read or modify and reg_val has the actual value of
440 adm1026_send8(adm1026_unit_t *unitp, uint8_t reg, uint8_t reg_val, argument
449 val |= (reg_val & reg_mask);
484 uint8_t reg_val = 0; local
488 err = adm1026_get8(unitp, ADM1026_STS_REG5, &reg_val);
492 *val = reg_val;
496 err = adm1026_get8(unitp, ADM1026_STS_REG6, &reg_val);
500 *val |= ((reg_val << OUTPUT_SHIFT) & (mask & 0xff00));
636 err = adm1026_set_output(unitp, g_buf.reg_val, g_bu
[all...]
H A Dpca9556.c74 * wants to read or modify and reg_val has the actual value of the
78 * and the values will be copied into reg_val.
715 g_buf.reg_val = g_buf.reg_mask &
730 (g_buf.reg_val & g_buf.reg_mask);
/opensolaris-onvv-gate/usr/src/uts/common/io/1394/targets/dcam1394/
H A Ddcam_param.c56 uint_t reg_val);
1705 feature_csr_val_subparam_extract(uint_t subparam, uint_t reg_val) argument
1712 ret_val = (reg_val & DCAM1394_MASK_PRESENCE_INQ) >>
1717 ret_val = (reg_val & DCAM1394_MASK_ON_OFF) >>
1722 ret_val = (reg_val & DCAM1394_MASK_A_M_MODE) >>
1727 ret_val = (reg_val & DCAM1394_MASK_VALUE) >>
1732 ret_val = (reg_val & DCAM1394_MASK_U_VALUE) >>
1738 ret_val = (reg_val & DCAM1394_MASK_V_VALUE) >>
1760 uint_t reg_val)
1767 ret_val = (reg_val
1759 feature_elm_inq_reg_val_subparam_extract(uint_t subparam, uint_t reg_val) argument
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/opensolaris-onvv-gate/usr/src/lib/libprtdiag_psr/sparc/opl/common/
H A Dopl_picl.c104 int *reg_val; local
196 reg_val = malloc(pinfo.size);
197 if (reg_val == NULL)
202 (nodeh, OBP_PROP_REG, reg_val, pinfo.size);
205 free(reg_val);
210 if (reg_val[0] != 0) {
212 (((reg_val[0]) & PCI_DEV_MASK) >> 11);
214 (((reg_val[0]) & PCI_FUNC_MASK) >> 8);
216 (((reg_val[0]) & PCI_BUS_MASK) >> 16);
218 free(reg_val);
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/opensolaris-onvv-gate/usr/src/uts/common/io/e1000g/
H A De1000g_rx.c147 uint32_t reg_val; local
344 reg_val =
348 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val);
355 reg_val = E1000_READ_REG(hw, E1000_RFCTL);
356 reg_val |= (E1000_RFCTL_IPV6_EX_DIS |
358 E1000_WRITE_REG(hw, E1000_RFCTL, reg_val);
/opensolaris-onvv-gate/usr/src/uts/common/io/chxge/
H A Dglue.c90 t1_read_reg_4(ch_t *obj, uint32_t reg_val) argument
92 return (ddi_get32(obj->ch_hbar0, (uint32_t *)(obj->ch_bar0 + reg_val)));
96 t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val) argument
98 ddi_put32(obj->ch_hbar0, (uint32_t *)(obj->ch_bar0+reg_val), write_val);
H A Dch.h285 uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);
286 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
/opensolaris-onvv-gate/usr/src/uts/common/io/
H A Dpci_cap.c201 * 16-bits of the cap header matches <reg_val> after masking the value
202 * with <reg_mask>; if both <reg_mask> and <reg_val> are 0, it will return
206 pci_htcap_locate(ddi_acc_handle_t h, uint16_t reg_mask, uint16_t reg_val, argument
235 reg_mask) == reg_val) {
/opensolaris-onvv-gate/usr/src/common/openssl/crypto/perlasm/
H A Dx86unix.pl75 %reg_val=(
258 $op=$special{$name}|$reg_val{$p1};
288 $op=$special{$name}|$reg_val{$p1};
/opensolaris-onvv-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_espc.c362 uint32_t reg_val = 0; local
365 reg_val = val & 0xffffffff;
367 return (reg_val);
/opensolaris-onvv-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hio_guest.c180 int *reg_val; local
206 0, "reg", &reg_val, &reg_len) != DDI_PROP_SUCCESS) {
211 cookie = (uint32_t)(reg_val[0]);
212 ddi_prop_free(reg_val);
/opensolaris-onvv-gate/usr/src/uts/common/sys/
H A Dpci_cap.h39 int pci_htcap_locate(ddi_acc_handle_t h, uint16_t reg_mask, uint16_t reg_val,
/opensolaris-onvv-gate/usr/src/cmd/picl/plugins/sun4u/mpxu/frudr/
H A Dpiclfrudr.c647 gpio.reg_val = (leds ^ 0xff);
650 gpio.reg_val = (leds ^ 0xff);
691 gpio.reg_val = BOSTON_FRONT_CLEAR_POL;
699 gpio.reg_val = BOSTON_FRONT_CLEAR_DIR;
707 gpio.reg_val = leds;
728 gpio.reg_val = BOSTON_REAR_CLEAR_POL;
736 gpio.reg_val = BOSTON_REAR_LED_MASK;
744 gpio.reg_val = leds;
/opensolaris-onvv-gate/usr/src/uts/common/io/igb/
H A Digb_gld.c505 uint32_t reg_val; local
514 reg_val = E1000_READ_REG(&igb->hw, E1000_RCTL);
517 reg_val |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
519 reg_val &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE));
521 E1000_WRITE_REG(&igb->hw, E1000_RCTL, reg_val);
H A Digb_main.c2116 uint32_t reg_val; local
2169 reg_val = E1000_READ_REG(hw,
2171 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2173 E1000_DCA_TXCTRL(tx_ring->index), reg_val);
2191 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
2192 reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
2193 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
2206 uint32_t reg_val; local
2217 reg_val = E1000_READ_REG(hw, E1000_TCTL);
2218 reg_val
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/opensolaris-onvv-gate/usr/src/uts/common/io/nge/
H A Dnge_chip.c676 uint32_t reg_val; local
698 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK);
699 reg_val &= ~NGE_INTR_ALL_EN;
700 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val);
/opensolaris-onvv-gate/usr/src/uts/common/io/ppm/
H A Dppm.c1716 i2c_req.reg_val = dc->m_un.i2c.val;
1804 *lvl = (i2c_req.reg_val == off_val) ? PPMD_OFF : PPMD_ON;
1807 (i2c_req.reg_val == off_val) ? "OFF" : "ON"))
2245 i2c_req.reg_val = dc->m_un.i2c.val;

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