Searched refs:PCIE_DBG (Results 1 - 9 of 9) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/common/io/pciex/hotplug/
H A Dpcishpc.c140 PCIE_DBG("pcishpc_init() called from %s#%d\n",
144 PCIE_DBG("pcishpc_init() shpc instance already "
153 PCIE_DBG("pcishpc_init() failed to create shpc softstate\n");
158 PCIE_DBG("pcishpc_init() failed to setup controller\n");
168 PCIE_DBG("%s%d: P2P bridge register dump:\n",
172 PCIE_DBG("SHPC Cfg reg 0x%02x: %08x\n", i,
180 PCIE_DBG("pcishpc_init() failed to register "
185 PCIE_DBG("pcishpc_init() failed to create "
196 PCIE_DBG("pcishpc_init() success(dip=%p)\n", dip);
222 PCIE_DBG("pcishpc_unini
[all...]
H A Dpciehpc.c129 PCIE_DBG("pciehpc_init() called (dip=%p)\n", (void *)dip);
133 PCIE_DBG("%s%d: pciehpc instance already initialized!\n",
221 PCIE_DBG("pciehpc_uninit() called (dip=%p)\n", (void *)dip);
308 PCIE_DBG("pciehpc_intr(): CMD COMPLETED interrupt received\n");
315 PCIE_DBG("pciehpc_intr(): ATTN BUTTON interrupt received\n");
330 PCIE_DBG("pciehpc_intr(): POWER FAULT interrupt received"
349 PCIE_DBG("pciehpc_intr(): MRL SENSOR CHANGED interrupt received"
356 PCIE_DBG("pciehpc_intr(): PRESENCE CHANGED interrupt received"
410 PCIE_DBG("pciehpc_intr(): DLL STATE CHANGED interrupt received"
435 PCIE_DBG("pciehpc_hp_op
[all...]
H A Dpcie_hp.c226 PCIE_DBG("pcie_hp_init: initialize hotplug "
330 PCIE_DBG("pcie_hp_probe() failed\n");
364 PCIE_DBG("pcie_hp_unprobe() failed\n");
908 PCIE_DBG("pcie_hp_common_ops: dip=%p cn_name=%s op=%x arg=%p\n",
927 PCIE_DBG("pcie_hp_common_ops: change port state"
/opensolaris-onvv-gate/usr/src/uts/intel/io/pciex/
H A Dpcie_acpi.c69 PCIE_DBG("No ACPI device found (dip %p)\n", (void *)dip);
78 PCIE_DBG("no _OSC method present for dip %p\n",
87 PCIE_DBG("Failed to evaluate _OSC method for dip 0x%p\n",
190 PCIE_DBG("Failed to execute _OSC method (status %d)\n",
200 PCIE_DBG("_OSC method failed (STATUS %d)\n", rbuf[0]);
207 PCIE_DBG("_OSC method evaluation completed for 0x%p: "
243 PCIE_DBG("PCIE BUS PATHNAME: %s\n", (char *)retbuf.Pointer);
247 PCIE_DBG(" METHODS: \n");
273 PCIE_DBG("%sDEVICE: %s\n", buf, (char *)retbuf.Pointer);
277 PCIE_DBG("
[all...]
/opensolaris-onvv-gate/usr/src/uts/intel/io/pciex/hotplug/
H A Dpciehpc_acpi.c140 PCIE_DBG("pciehpc_acpi_hpc_init: Get ACPI object failed\n");
278 PCIE_DBG("ACPI hot plug is enabled for slot #%d\n",
323 PCIE_DBG("slot %d already connected\n",
345 PCIE_DBG("slot %d is empty\n", slot_p->hs_phy_slot_num);
356 PCIE_DBG("slot %d already connected\n",
395 PCIE_DBG("slot %d already disconnected\n",
410 PCIE_DBG("slot %d is empty", slot_p->hs_phy_slot_num);
440 PCIE_DBG("install event handler for slot %d\n",
483 PCIE_DBG("received Notify(%d) event on slot #%d\n",
497 PCIE_DBG("(
[all...]
/opensolaris-onvv-gate/usr/src/uts/common/io/pciex/
H A Dpcie_pwr.c126 PCIE_DBG("%s(%d): pcie_power: change from %d to %d\n",
130 PCIE_DBG("%s(%d): pcie_power: already at %d\n",
142 PCIE_DBG("%s(%d): pcie_power: rejecting change to %d "
157 PCIE_DBG("%s(%d): pcie_power: rejecting level %d as"
166 PCIE_DBG("%s(%d): pcie_power: attempt to change to %d "
172 PCIE_DBG("%s(%d): pcie_power: level changed to %d \n",
220 PCIE_DBG("%s(%d): pwr_change: saving config space regs\n",
223 PCIE_DBG("%s(%d): pcie_pwr_change: failed to save "
245 PCIE_DBG("%s(%d): pcie_pwr_change: restoring config space\n",
248 PCIE_DBG("
[all...]
H A Dpcie.c225 PCIE_DBG("Failed to create devctl minor node for %s%d\n",
243 PCIE_DBG("%s%d: Failed setting hotplug framework\n",
266 PCIE_DBG("Failed to uninitialize hotplug for %s%d\n",
488 PCIE_DBG("%s: BUS not found.\n",
540 PCIE_DBG("No I/O range found for %s, bdf 0x%x\n",
546 PCIE_DBG("No Mem range found for %s, bdf 0x%x\n",
1182 PCIE_DBG("Add %s(dip 0x%p, bdf 0x%x, secbus 0x%x)\n",
1771 PCIE_DBG("%s: BUS not found.\n",
1862 PCIE_DBG("MPS: Highest Common MPS= %x\n", max_supported);
1905 PCIE_DBG("MP
[all...]
/opensolaris-onvv-gate/usr/src/uts/sparc/io/pciex/
H A Dpcie_sparc.c71 PCIE_DBG("%s(%d): can't create pm-want-child-notification \n",
/opensolaris-onvv-gate/usr/src/uts/common/sys/
H A Dpcie_impl.h477 #define PCIE_DBG pcie_dbg macro
480 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
484 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
488 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
495 #define PCIE_DBG 0 && macro

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