Searched refs:PCIEB_CACHE_LINE_SIZE (Results 1 - 2 of 2) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/common/io/pciex/
H A Dpcieb.h157 #define PCIEB_CACHE_LINE_SIZE 0x10 /* 64 bytes in # of DWORDs */ macro
H A Dpcieb.c1849 PCIEB_CACHE_LINE_SIZE);

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