Searched refs:HXGE_REG_WR32 (Results 1 - 8 of 8) sorted by relevance

/opensolaris-onvv-gate/usr/src/uts/common/io/hxge/
H A Dhpi_vir.c55 HXGE_REG_WR32(handle, LD_GRP_CTRL + LD_NUM_OFFSET(ld), gnum.value);
135 HXGE_REG_WR32(handle, offset, (uint32_t)ldf_mask);
170 HXGE_REG_WR32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), mgm.value);
197 HXGE_REG_WR32(handle, LD_INTR_TIM_RES, tm.value);
226 HXGE_REG_WR32(handle, SID + LDG_SID_OFFSET(sid.ldg), sd.value);
249 HXGE_REG_WR32(handle, DEV_ERR_MASK, dev_mask.value);
H A Dhxge_common_impl.h222 #define HXGE_REG_WR32(handle, offset, val) { \ macro
H A Dhxge_hw.c241 HXGE_REG_WR32(handle, PEU_INTR_MASK, 0xffffffff);
H A Dhxge_main.c720 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, 0x0000001E);
4478 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16, data0);
4479 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 4, data1);
4480 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 8, data2);
4481 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 12, 0);
H A Dhxge_pfc.c660 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
H A Dhxge_virtual.c654 HXGE_REG_WR32(hxgep->hpi_handle, PEU_INTR_MASK, parity_err_mask.value);
H A Dhxge_txdma.c99 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
2854 HXGE_REG_WR32(handle, BLOCK_RESET, reset_reg.value);
H A Dhxge_rxdma.c123 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
3747 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);

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