/opensolaris-onvv-gate/usr/src/uts/sun4u/io/pci/ |
H A D | pci_pwr.c | 86 DEBUG2(DBG_PWR, ddi_get_parent(dip), "ADDING NEW PWR_INFO %s@%s\n", 176 DEBUG3(DBG_PWR, ddi_get_parent(cdip), 287 DEBUG1(DBG_PWR, pwr_p->pwr_dip, "new_lvl: " 298 DEBUG1(DBG_PWR, pwr_p->pwr_dip, "new_lvl: unknown " 310 DEBUG1(DBG_PWR, pwr_p->pwr_dip, 315 DEBUG1(DBG_PWR, pwr_p->pwr_dip, 320 DEBUG1(DBG_PWR, pwr_p->pwr_dip, 325 DEBUG1(DBG_PWR, pwr_p->pwr_dip, 329 DEBUG0(DBG_PWR, pwr_p->pwr_dip, 364 DEBUG1(DBG_PWR, pwr_ [all...] |
H A D | pci_debug.c | 77 {DBG_PWR, "pwr"},
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H A D | pci_pci.c | 869 DEBUG2(DBG_PWR, ddi_get_parent(child), 877 DEBUG2(DBG_PWR, ddi_get_parent(child), 1018 DEBUG2(DBG_PWR, ddi_get_parent(dip), 1062 DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI" 1088 DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n"); 1091 DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n"); 1094 DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n"); 1097 DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n"); 1101 DEBUG0(DBG_PWR, pdip, 1104 DEBUG0(DBG_PWR, pdi [all...] |
H A D | pci_util.c | 377 DEBUG0(DBG_PWR, ddi_get_parent(child), "\n\n"); 505 DEBUG0(DBG_PWR, child, 511 DEBUG2(DBG_PWR, ddi_get_parent(child), 886 DEBUG2(DBG_PWR, dip,
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H A D | pcisch.c | 3519 DEBUG0(DBG_PWR, dip, "quiescing bus\n");
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/opensolaris-onvv-gate/usr/src/uts/sun4/io/px/ |
H A D | px_debug.h | 90 /* 43 */ DBG_PWR, enumerator in enum:__anon9818
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H A D | px.c | 340 DBG(DBG_PWR, dip, "pwr_common_setup failed\n"); 342 DBG(DBG_PWR, dip, "px_pwr_setup failed \n"); 629 DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n"); 653 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add " 663 DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt" 1274 DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n", 1280 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n", 1289 DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n", 1323 DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
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H A D | px_util.c | 385 DBG(DBG_PWR, ddi_get_parent(child), "\n\n"); 503 DBG(DBG_PWR, parent_dip, 517 DBG(DBG_PWR, child, 523 DBG(DBG_PWR, parent_dip,
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/opensolaris-onvv-gate/usr/src/uts/common/io/pciex/ |
H A D | pcieb.c | 423 PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n"); 428 PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n"); 849 PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip, 864 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 873 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 1553 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup " 1564 PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. " 1575 PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n"); 1579 PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n"); 1597 PCIEB_DEBUG(DBG_PWR, di [all...] |
H A D | pcieb.h | 41 /* 1 */ DBG_PWR, enumerator in enum:__anon6587
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/opensolaris-onvv-gate/usr/src/uts/sun4u/sys/pci/ |
H A D | pci_debug.h | 85 #define DBG_PWR (0x8000ull << 32) macro
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/opensolaris-onvv-gate/usr/src/uts/sun4u/io/px/ |
H A D | px_lib4u.c | 1842 DBG(DBG_PWR, px_p->px_dip, 1847 DBG(DBG_PWR, px_p->px_dip, "ioctl: PRE_PWR_ON request\n"); 1851 DBG(DBG_PWR, px_p->px_dip, "ioctl: POST_PWR_ON request\n"); 1935 DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting" 1951 DBG(DBG_PWR, px_p->px_dip, " Link is not at L1" 1982 DBG(DBG_PWR, px_p->px_dip, " PME_To_ACK received \n");
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H A D | px_hlib.c | 2995 DBG(DBG_PWR, NULL, "send_pme_turnoff: pending PTO bit " 3025 DBG(DBG_PWR, NULL, "check_for_l1idle: ltssm_state %x\n", ltssm_state); 3039 DBG(DBG_PWR, NULL, "retrain_link: detect.quiet bit not set\n");
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