H A D | SPARCAssembler.java | 888 private static final BitSpec rs2 = new ContinousBitSpec(4, 0, "rs2"); field in class:SPARCAssembler.BitSpec 1413 public void emit(SPARCMacroAssembler masm, ConditionFlag cf, boolean cc2, Register rs1, Register rs2, Label lab) { argument 1415 inst = BitSpec.rs2.setBits(inst, rs2.encoding); 1506 public static void emit(SPARCMacroAssembler masm, Op3s opcode, Register rs1, Register rs2, Register rd) { argument 1508 instruction = BitSpec.rs2.setBits(instruction, rs2.encoding); 1556 void emit(SPARCMacroAssembler masm, ConditionFlag condition, CC cc, Register rs2, Register rd); argument 1569 public void emit(SPARCMacroAssembler masm, ConditionFlag condition, CC cc, Register rs2, Registe argument 1609 emit(SPARCMacroAssembler masm, ConditionFlag condition, CC cc, Register rs2, Register rd) argument 1653 emit(SPARCMacroAssembler masm, Opfs opf, Register rs1, Register rs2, Register rd) argument 1660 emitFcmp(SPARCMacroAssembler masm, Opfs opf, CC cc, Register rs1, Register rs2) argument 1667 setBits(int instruction, Opfs opf, Register rs1, Register rs2) argument 1822 op3(Op3s op3, Opfs opf, Register rs1, Register rs2, Register rd) argument 1827 op3(Op3s op3, Register rs1, Register rs2, Register rd) argument 1894 add(Register rs1, Register rs2, Register rd) argument 1902 addc(Register rs1, Register rs2, Register rd) argument 1910 addcc(Register rs1, Register rs2, Register rd) argument 1918 and(Register rs1, Register rs2, Register rd) argument 1926 andcc(Register rs1, Register rs2, Register rd) argument 1934 andn(Register rs1, Register rs2, Register rd) argument 1942 andncc(Register rs1, Register rs2, Register rd) argument 1950 movwtos(Register rs2, Register rd) argument 1955 umulxhi(Register rs1, Register rs2, Register rd) argument 1959 fdtos(Register rs2, Register rd) argument 1964 movstouw(Register rs2, Register rd) argument 1969 movstosw(Register rs2, Register rd) argument 1974 movdtox(Register rs2, Register rd) argument 1979 movxtod(Register rs2, Register rd) argument 1984 fadds(Register rs1, Register rs2, Register rd) argument 1988 faddd(Register rs1, Register rs2, Register rd) argument 1992 fdivs(Register rs1, Register rs2, Register rd) argument 1996 fdivd(Register rs1, Register rs2, Register rd) argument 2000 fmovs(Register rs2, Register rd) argument 2004 fmovd(Register rs2, Register rd) argument 2008 fsrc2s(Register rs2, Register rd) argument 2012 fsrc2d(Register rs2, Register rd) argument 2016 fmuls(Register rs1, Register rs2, Register rd) argument 2020 fsmuld(Register rs1, Register rs2, Register rd) argument 2024 fmuld(Register rs1, Register rs2, Register rd) argument 2028 fnegs(Register rs2, Register rd) argument 2032 fnegd(Register rs2, Register rd) argument 2050 fstoi(Register rs2, Register rd) argument 2054 fstox(Register rs2, Register rd) argument 2058 fdtox(Register rs2, Register rd) argument 2062 fstod(Register rs2, Register rd) argument 2066 fdtoi(Register rs2, Register rd) argument 2070 fitos(Register rs2, Register rd) argument 2074 fitod(Register rs2, Register rd) argument 2078 fxtos(Register rs2, Register rd) argument 2082 fxtod(Register rs2, Register rd) argument 2098 fsqrtd(Register rs2, Register rd) argument 2102 fsqrts(Register rs2, Register rd) argument 2106 fabss(Register rs2, Register rd) argument 2110 fabsd(Register rs2, Register rd) argument 2114 fsubs(Register rs1, Register rs2, Register rd) argument 2118 fsubd(Register rs1, Register rs2, Register rd) argument 2131 fcmp(CC cc, Opfs opf, Register rs1, Register rs2) argument 2170 jmpl(Register rs1, Register rs2, Register rd) argument 2185 fmovdcc(ConditionFlag cond, CC cc, Register rs2, Register rd) argument 2189 fmovscc(ConditionFlag cond, CC cc, Register rs2, Register rd) argument 2193 fmovcc(ConditionFlag cond, CC cc, Register rs2, Register rd, int opfLow) argument 2199 movcc(ConditionFlag conditionFlag, CC cc, Register rs2, Register rd) argument 2216 mulx(Register rs1, Register rs2, Register rd) argument 2224 or(Register rs1, Register rs2, Register rd) argument 2234 popc(Register rs2, Register rd) argument 2260 restore(Register rs1, Register rs2, Register rd) argument 2266 save(Register rs1, Register rs2, Register rd) argument 2274 sdivx(Register rs1, Register rs2, Register rd) argument 2282 udivx(Register rs1, Register rs2, Register rd) argument 2290 sll(Register rs1, Register rs2, Register rd) argument 2299 sllx(Register rs1, Register rs2, Register rd) argument 2308 sra(Register rs1, Register rs2, Register rd) argument 2316 srax(Register rs1, Register rs2, Register rd) argument 2325 srl(Register rs1, Register rs2, Register rd) argument 2333 srlx(Register rs1, Register rs2, Register rd) argument 2342 sub(Register rs1, Register rs2, Register rd) argument 2350 subcc(Register rs1, Register rs2, Register rd) argument 2377 wrccr(Register rs1, Register rs2) argument 2385 xor(Register rs1, Register rs2, Register rd) argument 2393 xorcc(Register rs1, Register rs2, Register rd) argument 2401 xnor(Register rs1, Register rs2, Register rd) argument 2553 ldxa(Register rs1, Register rs2, Register rd, Asi asi) argument 2558 lduwa(Register rs1, Register rs2, Register rd, Asi asi) argument 2563 stxa(Register rd, Register rs1, Register rs2, Asi asi) argument 2606 casa(Register rs1, Register rs2, Register rd, Asi asi) argument 2610 casxa(Register rs1, Register rs2, Register rd, Asi asi) argument 2630 fpadd32(Register rs1, Register rs2, Register rd) argument [all...] |