Searched refs:rs2 (Results 1 - 10 of 10) sorted by relevance

/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.sparc/src/org/graalvm/compiler/lir/sparc/
H A DSPARCOP3Op.java54 @Use({REG, CONST}) protected Value rs2; field in class:SPARCOP3Op
58 public static SPARCOP3Op newUnary(Op3s op3, Value rs2, AllocatableValue rd) { argument
59 return newUnary(op3, rs2, rd, null);
62 public static SPARCOP3Op newUnary(Op3s op3, Value rs2, AllocatableValue rd, LIRFrameState state) { argument
63 return new SPARCOP3Op(op3, g0.asValue(LIRKind.value(rs2.getPlatformKind())), rs2, rd, state);
66 public static SPARCOP3Op newBinaryVoid(Op3s op3, AllocatableValue rs1, Value rs2) { argument
67 return newBinaryVoid(op3, rs1, rs2, null);
70 public static SPARCOP3Op newBinaryVoid(Op3s op3, AllocatableValue rs1, Value rs2, LIRFrameState state) { argument
71 return new SPARCOP3Op(op3, rs1, rs2, g
74 SPARCOP3Op(Op3s op3, AllocatableValue rs1, Value rs2, AllocatableValue rd) argument
78 SPARCOP3Op(Op3s op3, AllocatableValue rs1, Value rs2, AllocatableValue rd, LIRFrameState state) argument
96 emitOp3(SPARCMacroAssembler masm, Op3s op3, Value rs1, Value rs2) argument
100 emitOp3(SPARCMacroAssembler masm, Op3s op3, Value rs1, Value rs2, Value rd) argument
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H A DSPARCOPFOp.java47 @Use({REG}) protected AllocatableValue rs2; field in class:SPARCOPFOp
51 public SPARCOPFOp(Opfs opf, AllocatableValue rs2, AllocatableValue rd) { argument
52 this(opf, SPARC.g0.asValue(LIRKind.value(SPARCKind.SINGLE)), rs2, rd);
55 public SPARCOPFOp(Opfs opf, AllocatableValue rs1, AllocatableValue rs2, AllocatableValue rd) { argument
56 this(opf, rs1, rs2, rd, null);
59 public SPARCOPFOp(Opfs opf, AllocatableValue rs1, AllocatableValue rs2, AllocatableValue rd, LIRFrameState state) { argument
63 this.rs2 = rs2;
74 SPARCAssembler.OpfOp.emit(masm, opf, asRegister(rs1), asRegister(rs2), asRegister(rd));
H A DSPARCControlFlow.java297 Register rs2 = scratch.getRegister();
298 masm.setx(constantY, rs2, false);
299 CBCOND.emit(masm, cFlag, isLong, rs1, rs2, actualTrueTarget);
303 Register rs2 = asRegister(actualY, xKind);
304 CBCOND.emit(masm, cFlag, isLong, rs1, rs2, actualTrueTarget);
/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.sparc/src/org/graalvm/compiler/asm/sparc/
H A DSPARCAssembler.java888 private static final BitSpec rs2 = new ContinousBitSpec(4, 0, "rs2"); field in class:SPARCAssembler.BitSpec
1413 public void emit(SPARCMacroAssembler masm, ConditionFlag cf, boolean cc2, Register rs1, Register rs2, Label lab) { argument
1415 inst = BitSpec.rs2.setBits(inst, rs2.encoding);
1506 public static void emit(SPARCMacroAssembler masm, Op3s opcode, Register rs1, Register rs2, Register rd) { argument
1508 instruction = BitSpec.rs2.setBits(instruction, rs2.encoding);
1556 void emit(SPARCMacroAssembler masm, ConditionFlag condition, CC cc, Register rs2, Register rd); argument
1569 public void emit(SPARCMacroAssembler masm, ConditionFlag condition, CC cc, Register rs2, Registe argument
1609 emit(SPARCMacroAssembler masm, ConditionFlag condition, CC cc, Register rs2, Register rd) argument
1653 emit(SPARCMacroAssembler masm, Opfs opf, Register rs1, Register rs2, Register rd) argument
1660 emitFcmp(SPARCMacroAssembler masm, Opfs opf, CC cc, Register rs1, Register rs2) argument
1667 setBits(int instruction, Opfs opf, Register rs1, Register rs2) argument
1822 op3(Op3s op3, Opfs opf, Register rs1, Register rs2, Register rd) argument
1827 op3(Op3s op3, Register rs1, Register rs2, Register rd) argument
1894 add(Register rs1, Register rs2, Register rd) argument
1902 addc(Register rs1, Register rs2, Register rd) argument
1910 addcc(Register rs1, Register rs2, Register rd) argument
1918 and(Register rs1, Register rs2, Register rd) argument
1926 andcc(Register rs1, Register rs2, Register rd) argument
1934 andn(Register rs1, Register rs2, Register rd) argument
1942 andncc(Register rs1, Register rs2, Register rd) argument
1950 movwtos(Register rs2, Register rd) argument
1955 umulxhi(Register rs1, Register rs2, Register rd) argument
1959 fdtos(Register rs2, Register rd) argument
1964 movstouw(Register rs2, Register rd) argument
1969 movstosw(Register rs2, Register rd) argument
1974 movdtox(Register rs2, Register rd) argument
1979 movxtod(Register rs2, Register rd) argument
1984 fadds(Register rs1, Register rs2, Register rd) argument
1988 faddd(Register rs1, Register rs2, Register rd) argument
1992 fdivs(Register rs1, Register rs2, Register rd) argument
1996 fdivd(Register rs1, Register rs2, Register rd) argument
2000 fmovs(Register rs2, Register rd) argument
2004 fmovd(Register rs2, Register rd) argument
2008 fsrc2s(Register rs2, Register rd) argument
2012 fsrc2d(Register rs2, Register rd) argument
2016 fmuls(Register rs1, Register rs2, Register rd) argument
2020 fsmuld(Register rs1, Register rs2, Register rd) argument
2024 fmuld(Register rs1, Register rs2, Register rd) argument
2028 fnegs(Register rs2, Register rd) argument
2032 fnegd(Register rs2, Register rd) argument
2050 fstoi(Register rs2, Register rd) argument
2054 fstox(Register rs2, Register rd) argument
2058 fdtox(Register rs2, Register rd) argument
2062 fstod(Register rs2, Register rd) argument
2066 fdtoi(Register rs2, Register rd) argument
2070 fitos(Register rs2, Register rd) argument
2074 fitod(Register rs2, Register rd) argument
2078 fxtos(Register rs2, Register rd) argument
2082 fxtod(Register rs2, Register rd) argument
2098 fsqrtd(Register rs2, Register rd) argument
2102 fsqrts(Register rs2, Register rd) argument
2106 fabss(Register rs2, Register rd) argument
2110 fabsd(Register rs2, Register rd) argument
2114 fsubs(Register rs1, Register rs2, Register rd) argument
2118 fsubd(Register rs1, Register rs2, Register rd) argument
2131 fcmp(CC cc, Opfs opf, Register rs1, Register rs2) argument
2170 jmpl(Register rs1, Register rs2, Register rd) argument
2185 fmovdcc(ConditionFlag cond, CC cc, Register rs2, Register rd) argument
2189 fmovscc(ConditionFlag cond, CC cc, Register rs2, Register rd) argument
2193 fmovcc(ConditionFlag cond, CC cc, Register rs2, Register rd, int opfLow) argument
2199 movcc(ConditionFlag conditionFlag, CC cc, Register rs2, Register rd) argument
2216 mulx(Register rs1, Register rs2, Register rd) argument
2224 or(Register rs1, Register rs2, Register rd) argument
2234 popc(Register rs2, Register rd) argument
2260 restore(Register rs1, Register rs2, Register rd) argument
2266 save(Register rs1, Register rs2, Register rd) argument
2274 sdivx(Register rs1, Register rs2, Register rd) argument
2282 udivx(Register rs1, Register rs2, Register rd) argument
2290 sll(Register rs1, Register rs2, Register rd) argument
2299 sllx(Register rs1, Register rs2, Register rd) argument
2308 sra(Register rs1, Register rs2, Register rd) argument
2316 srax(Register rs1, Register rs2, Register rd) argument
2325 srl(Register rs1, Register rs2, Register rd) argument
2333 srlx(Register rs1, Register rs2, Register rd) argument
2342 sub(Register rs1, Register rs2, Register rd) argument
2350 subcc(Register rs1, Register rs2, Register rd) argument
2377 wrccr(Register rs1, Register rs2) argument
2385 xor(Register rs1, Register rs2, Register rd) argument
2393 xorcc(Register rs1, Register rs2, Register rd) argument
2401 xnor(Register rs1, Register rs2, Register rd) argument
2553 ldxa(Register rs1, Register rs2, Register rd, Asi asi) argument
2558 lduwa(Register rs1, Register rs2, Register rd, Asi asi) argument
2563 stxa(Register rd, Register rs1, Register rs2, Asi asi) argument
2606 casa(Register rs1, Register rs2, Register rd, Asi asi) argument
2610 casxa(Register rs1, Register rs2, Register rd, Asi asi) argument
2630 fpadd32(Register rs1, Register rs2, Register rd) argument
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H A DSPARCMacroAssembler.java112 public void cas(Register rs1, Register rs2, Register rd) { argument
113 casa(rs1, rs2, rd, Asi.ASI_PRIMARY);
116 public void casx(Register rs1, Register rs2, Register rd) { argument
117 casxa(rs1, rs2, rd, Asi.ASI_PRIMARY);
136 public void cmp(Register rs1, Register rs2) { argument
137 subcc(rs1, rs2, g0);
299 public void compareBranch(Register rs1, Register rs2, ConditionFlag cond, CC ccRegister, Label label, BranchPredict predict, Runnable delaySlotInstruction) { argument
300 assert isCPURegister(rs1, rs2);
306 CBCOND.emit(this, cond, ccRegister == Xcc, rs1, rs2, label);
311 cmp(rs1, rs2);
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/openjdk10/hotspot/src/cpu/sparc/vm/
H A Dassembler_sparc.inline.hpp86 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2));
93 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
99 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | rs2(s2));
105 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
227 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2));
258 emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2));
261 emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2));
265 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2));
271 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2));
277 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s
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H A Dassembler_sparc.hpp442 static int rs2(Register r) { return u_field(r->encoding(), 4, 0); } function in class:Assembler
/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/
H A DAArch64Assembler.java333 private static int rs2(Register reg) { method in class:AArch64Assembler
1142 emitInt(memop | LoadStoreRegisterOp | rs2(address.getOffset()) | extendType.encoding << ExtendTypeOffset | (shouldScale ? 1 : 0) << LoadStoreScaledRegOffset | rs1(address.getBase()));
1311 emitInt(transferSizeEncoding | instr.encoding | rs2(rs) | rn(rn) | rt(rt));
1635 emitInt(type.encoding | EXTR.encoding | sf | lsb << ImmediateOffset | rd(dst) | rs1(src1) | rs2(src2));
1699 emitInt(type.encoding | instr.encoding | AddSubShiftedOp | imm << ImmediateOffset | shiftType.encoding << ShiftTypeOffset | rd(dst) | rs1(src1) | rs2(src2));
1773 emitInt(type.encoding | instr.encoding | AddSubExtendedOp | shiftAmt << ImmediateOffset | extendType.encoding << ExtendTypeOffset | rd(dst) | rs1(src1) | rs2(src2));
1894 emitInt(type.encoding | instr.encoding | LogicalShiftOp | shiftAmt << ImmediateOffset | shiftType.encoding << ShiftTypeOffset | rd(dst) | rs1(src1) | rs2(src2));
2044 emitInt(type.encoding | instr.encoding | ConditionalSelectOp | rd(dst) | rs1(src1) | rs2(src2) | condition.encoding << ConditionalConditionOffset);
2086 emitInt(0b10011011010 << 21 | dst.encoding | rs1(src1) | rs2(src2) | 0b011111 << ImmediateOffset);
2100 emitInt(0b10011011110 << 21 | dst.encoding | rs1(src1) | rs2(src
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/openjdk10/hotspot/test/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/sparc/
H A DSPARCTestAssembler.java64 private void emitOp3(int op, Register rd, int op3, Register rs1, Register rs2) { argument
65 code.emitInt((op << 30) | (rd.encoding << 25) | (op3 << 19) | (rs1.encoding << 14) | rs2.encoding);
/openjdk10/jdk/src/java.sql.rowset/share/classes/com/sun/rowset/internal/
H A DCachedRowSetWriter.java832 ResultSet rs2 = con.getMetaData().getPrimaryKeys(null, null,
840 while (rs2.next()) {
841 primaryKeys[k] = rs2.getString("COLUMN_NAME");

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