Searched refs:wm_table (Results 1 - 19 of 19) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.h33 extern struct wm_table ddr4_wm_table_gs;
34 extern struct wm_table lpddr4_wm_table_gs;
35 extern struct wm_table lpddr4_wm_table_with_disabled_ppt;
36 extern struct wm_table ddr4_wm_table_rn;
37 extern struct wm_table ddr4_1R_wm_table_rn;
38 extern struct wm_table lpddr4_wm_table_rn;
H A Drn_clk_mgr.c462 if (!bw_params->wm_table.entries[i].valid)
465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
677 bw_params->wm_table.entries[i].wm_inst = i;
680 bw_params->wm_table.entries[i].valid = false;
684 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
685 bw_params->wm_table.entries[i].valid = true;
745 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
748 rn_bw_params.wm_table = lpddr4_wm_table_gs;
750 rn_bw_params.wm_table
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.h32 extern struct wm_table ddr4_wm_table;
33 extern struct wm_table lpddr5_wm_table;
H A Dvg_clk_mgr.c394 if (!bw_params->wm_table.entries[i].valid)
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
601 bw_params->wm_table.entries[i].wm_inst = i;
604 bw_params->wm_table.entries[i].valid = false;
608 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
609 bw_params->wm_table.entries[i].valid = true;
718 vg_bw_params.wm_table = lpddr5_wm_table;
720 vg_bw_params.wm_table = ddr4_wm_table;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
413 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
432 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
437 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
438 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
439 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
459 if (dc->clk_mgr->bw_params->wm_table
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h215 struct wm_table { struct
235 struct wm_table wm_table; member in struct:clk_bw_params
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c265 static struct wm_table ddr4_wm_table = {
302 static struct wm_table lpddr5_wm_table = {
351 if (!bw_params->wm_table.entries[i].valid)
354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
547 bw_params->wm_table.entries[i].wm_inst = i;
550 bw_params->wm_table.entries[i].valid = false;
554 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
555 bw_params->wm_table.entries[i].valid = true;
634 dcn316_bw_params.wm_table
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
200 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
202 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
203 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
205 clk_mgr->base.bw_params->wm_table
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c218 struct wm_table ddr4_wm_table = {
255 struct wm_table lpddr5_wm_table = {
429 table_entry = &bw_params->wm_table.entries[WM_D];
437 table_entry = &bw_params->wm_table.entries[WM_C];
442 table_entry = &bw_params->wm_table.entries[WM_B];
448 table_entry = &bw_params->wm_table.entries[WM_A];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c343 static struct wm_table ddr5_wm_table = {
380 static struct wm_table lpddr5_wm_table = {
429 if (!bw_params->wm_table.entries[i].valid)
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
619 bw_params->wm_table.entries[i].wm_inst = i;
622 bw_params->wm_table.entries[i].valid = false;
626 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
627 bw_params->wm_table.entries[i].valid = true;
727 dcn31_bw_params.wm_table
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c358 static struct wm_table ddr5_wm_table = {
395 static struct wm_table lpddr5_wm_table = {
444 if (!bw_params->wm_table.entries[i].valid)
447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
692 bw_params->wm_table.entries[i].wm_inst = i;
695 bw_params->wm_table.entries[i].valid = false;
699 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
700 bw_params->wm_table.entries[i].valid = true;
771 dcn314_bw_params.wm_table
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c303 static struct wm_table ddr5_wm_table = {
340 static struct wm_table lpddr5_wm_table = {
389 if (!bw_params->wm_table.entries[i].valid)
392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
572 bw_params->wm_table.entries[i].wm_inst = i;
575 bw_params->wm_table.entries[i].valid = false;
579 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
580 bw_params->wm_table.entries[i].valid = true;
655 dcn315_bw_params.wm_table
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c340 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
341 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
342 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
343 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
344 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
346 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
459 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
460 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
461 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
474 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c765 struct wm_table ddr4_wm_table_gs = {
802 struct wm_table lpddr4_wm_table_gs = {
839 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
876 struct wm_table ddr4_wm_table_rn = {
913 struct wm_table ddr4_1R_wm_table_rn = {
950 struct wm_table lpddr4_wm_table_rn = {
2176 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
2183 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
2194 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
2289 table_entry = &bw_params->wm_table
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c796 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
798 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c2553 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local
2558 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
H A Dvega20_hwmgr.c3645 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local
3650 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
H A Dvega10_hwmgr.c4926 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local
4931 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);

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