/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.h | 33 struct dcn315_watermarks *wm_set; member in struct:dcn315_smu_watermark_set
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H A D | dcn315_clk_mgr.c | 440 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set; 624 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem( 630 if (!clk_mgr->smu_wm_set.wm_set) { 631 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 634 ASSERT(clk_mgr->smu_wm_set.wm_set); 732 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 734 clk_mgr->smu_wm_set.wm_set);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.h | 33 struct dcn316_watermarks *wm_set; member in struct:dcn316_smu_watermark_set
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H A D | dcn316_clk_mgr.c | 402 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; 594 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem( 600 if (!clk_mgr->smu_wm_set.wm_set) { 601 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 604 ASSERT(clk_mgr->smu_wm_set.wm_set); 671 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 673 clk_mgr->smu_wm_set.wm_set);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.h | 36 struct watermarks *wm_set; member in struct:smu_watermark_set
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H A D | vg_clk_mgr.c | 446 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; 680 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem( 686 if (!clk_mgr->smu_wm_set.wm_set) { 687 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 690 ASSERT(clk_mgr->smu_wm_set.wm_set); 747 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 749 clk_mgr->smu_wm_set.wm_set);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_clk_mgr.h | 34 struct dcn314_watermarks *wm_set; member in struct:dcn314_smu_watermark_set
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H A D | dcn314_clk_mgr.c | 495 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; 737 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem( 743 if (!clk_mgr->smu_wm_set.wm_set) { 744 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 747 ASSERT(clk_mgr->smu_wm_set.wm_set); 847 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 849 clk_mgr->smu_wm_set.wm_set);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_clk_mgr.h | 33 struct dcn31_watermarks *wm_set; member in struct:dcn31_smu_watermark_set
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H A D | dcn31_clk_mgr.c | 480 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; 693 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( 699 if (!clk_mgr->smu_wm_set.wm_set) { 700 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 703 ASSERT(clk_mgr->smu_wm_set.wm_set); 804 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 806 clk_mgr->smu_wm_set.wm_set);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.c | 294 struct dcn_watermarks *wm_set, 311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 312 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 317 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 318 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 292 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/hw/ |
H A D | dchubbub.h | 44 uint32_t wm_set; member in struct:dcn_hubbub_wm_set
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/ |
H A D | dcn20_hubbub.c | 495 s->wm_set = 0; 506 s->wm_set = 1; 517 s->wm_set = 2; 528 s->wm_set = 3;
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn21/ |
H A D | dcn21_hubbub.c | 627 s->wm_set = 0; 641 s->wm_set = 1; 655 s->wm_set = 2; 669 s->wm_set = 3;
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/ |
H A D | dcn10_hubbub.c | 51 s->wm_set = 0; 61 s->wm_set = 1; 71 s->wm_set = 2; 81 s->wm_set = 3;
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H A D | dcn10_hw_sequencer_debug.c | 97 s->wm_set,
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H A D | dcn10_hw_sequencer.c | 156 DTN_INFO("WM_Set[%d]:", s->wm_set);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/ |
H A D | dcn32_hubbub.c | 857 s->wm_set = 0; 877 s->wm_set = 1; 897 s->wm_set = 2; 917 s->wm_set = 3;
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 2202 struct dcn_watermarks *wm_set, 2219 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 2220 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 2221 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 2222 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 2223 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 2224 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 2225 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 2226 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 2200 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
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/openbsd-current/usr.bin/vi/vi/ |
H A D | v_txt.c | 267 int wm_set, wm_skip; /* Wrapmargin happened, blank skip flags. */ local 408 wm_set = wm_skip = 0; 801 if (wm_set) { 813 wm_set = 0; 1317 wm_set = 1;
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